Nitish Natu - IEEE Xplore Author Profile
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Nitish Natu

Publications
3
Citations
11
Publications by Year
20132015
Co-Authors:
Show All Co-Authors (6)
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Nitish Natu

Affiliation

Oracle
Santa Clara
CA, USA
Georgia Institute of Technology
Atlanta
GA, USA

Publication Topics

Biography

Nitish Natu received the master’s degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2014.,He was part of the Mixed Signal Design Group and completed his thesis under Prof. M. Swaminathan. He has been a Hardware Developer with Oracle, Santa Clara, CA, USA.(Based on document published on 14 October 2015).
Publications
3
Citations
11
Publications by Year
20132015
Co-Authors:
Show All Co-Authors (6)
Author's Published Works

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Analysis, Design, and Prototyping of Temperature Resilient Clock Distribution Networks for 3-D ICs

Sung Joo Park;Nitish Natu;Madhavan Swaminathan

IEEE Transactions on Components, Packaging and Manufacturing Technology
Year: 2015 | Volume: 5, Issue: 11 | Journal Article |
Cited by: Papers (7)
The 3-D integrated circuits (3-D ICs) overcome the bottlenecks in system performance and circuit density. However, their increased power and thermal density cause temperature gradients in the chip that significantly affect signal and power integrity. Temperature gradients significantly degrade the clock signal, a key signal in digital systems, which in turn degrades system performance. In this pap...Show More

Analysis, Design, and Prototyping of Temperature Resilient Clock Distribution Networks for 3-D ICs

Sung Joo Park;Nitish Natu;Madhavan Swaminathan

Year: 2015 | Volume: 5, Issue: 11 | Journal Article |

Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs

Sung Joo Park;Madhavan Swaminathan;Nitish Natu;Byunghyun Lee;Sang Min Lee;Woong Hwan Ryu;Kee Sup Kim

2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems
Year: 2014 | Conference Paper |
Cited by: Papers (1)
Clock Distribution Networks (CDN) in three dimensional ICs face problems due to temperature and gradients observed across the die. The propagation delay of paths in the CDN varies and leads to mismatch in skew at the distribution points. This could potentially harm the system by violating setup and hold timing constraints. Compensation techniques can however be integrated with the CDN to compensat...Show More

Design and early validation (using FPGA) of temperature resilient clock distribution networks for 3D ICs

Sung Joo Park;Madhavan Swaminathan;Nitish Natu;Byunghyun Lee;Sang Min Lee;Woong Hwan Ryu;Kee Sup Kim

Year: 2014 | Conference Paper |

Timing analysis for thermally robust clock distribution network design for 3D ICs

Sung Joo Park;Nitish Natu;Madhavan Swaminathan;Byunghyun Lee;Sang Min Lee;Woong Hwan Ryu;Kee Sup Kim

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems
Year: 2013 | Conference Paper |
Cited by: Papers (3)
Three-dimensional Integrated Circuits provide a solution to overcome bottlenecks in performance and power management issues. However, the drawback arises in the form of increased thermal density that results in thermal gradients that affect signal integrity. Since, the clock signal is critical for ensuring the performance of synchronous digital systems, its design is very important. In this paper ...Show More

Timing analysis for thermally robust clock distribution network design for 3D ICs

Sung Joo Park;Nitish Natu;Madhavan Swaminathan;Byunghyun Lee;Sang Min Lee;Woong Hwan Ryu;Kee Sup Kim

Year: 2013 | Conference Paper |

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