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Ge/Si Heterojunction Tunnel Field-Effect Transistors and Their Post Metallization Annealing Effect | IEEE Journals & Magazine | IEEE Xplore

Ge/Si Heterojunction Tunnel Field-Effect Transistors and Their Post Metallization Annealing Effect


Abstract:

Ge/Si heterojunction tunnel field-effect transistors (TFETs) with an Al2O3 gate-stack are demonstrated. The high performances of steep subthreshold swing (SS) of 58 mV/de...Show More

Abstract:

Ge/Si heterojunction tunnel field-effect transistors (TFETs) with an Al2O3 gate-stack are demonstrated. The high performances of steep subthreshold swing (SS) of 58 mV/decade and large ION/IOFF ratio over 107 are realized by a proper postmetallization annealing (PMA) process. We can obtain the high-quality Al2O3/Ge interface with Dit of as low as ~1011 cm-2eV-1 by electron cyclotron resonance oxygen plasma post oxidation. The electrical characteristics of the Ge/SOI TFETs are studied with changing PMA temperature from 200 °C to 400 °C. It is found that Dit between Al2O3 and the Si channel region is a critical factor for significantly reducing SS of Ge/Si heterojunction TFETs.
Published in: IEEE Transactions on Electron Devices ( Volume: 62, Issue: 1, January 2015)
Page(s): 9 - 15
Date of Publication: 10 December 2014

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I. Introduction

Tunnel field-effect transistors (TFETs) have been regarded as one of promising devices for the next-generation low-power logic applications because of the limitation of the subthreshold swing (SS) in MOSFETs [1], [2]. However, contrary to the theoretical and simulation expectations, the experimental achievements of the high performance with steep SS are still difficult. Homojunction TFETs composed of a single material such as Si have difficulties in simultaneously obtaining high drain ON-current/OFF-current ratio (/ and steep SS, because of the limitation in the physical properties such as the energy bandgap [3]–[9]. Thus, heterojunction structures with various materials, which have different bandgap energy and band alignment, have recently been investigated to enhance the tunneling probability without causing the ambipolar action [10]–[13]. Above all, TFETs using Ge/Si heterojunction have attracted much attention because the smaller bandgap of the Ge-source and the band-offset of the Ge/Si heterojunction can increase the tunneling probability [14]–[16]. In addition, the Ge/Si heterojunctions can still maintain the process compatibility with the conventional CMOS. Moreover, the larger bandgap of the Si channel and drain can suppress the leakage current in the drain of nTFETs. However, large lattice mismatch between Ge and Si makes formation of a Ge/Si heterojunction difficult [17] and, therefore, the experimental results of TFETs with the SiGe/Si heterojunction have been reported more than those of TFETs with a pure-Ge/Si heterojunction [18]–[20].

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