I. Introduction
Common double-gate (CDG) MOSFETs have appeared as a replacement for bulk MOSFETs in sub-32-nm technology nodes [1], [2] due to their superior electrostatic integrity. Efficient compact models are required for successful utilization of such devices in integrated circuit design. Existing compact models for CDG-MOSFETs [3]–[7] are based on the fundamental assumption of having symmetric gate oxide thickness, as it greatly simplifies the model development process. However, the models could be generalized by considering the asymmetry between gate oxide thickness as there could be a possibility of having asymmetry between the gate oxide thickness due to process variations and uncertainties, which can affect device performance significantly. A similar problem is addressed in [8] for independent gate configuration with the back gate oxide thickness much higher than that of the front gate, electrostatic of which is quite different than that of the CDG device with comparable oxide thickness.