Abstract:
Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high p...Show MoreMetadata
Abstract:
Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices.
Published in: IEEE Transactions on Electron Devices ( Volume: 45, Issue: 3, March 1998)
DOI: 10.1109/16.661232
References is not available for this document.
Select All
1.
M. Aoki, T. Ishii, T. Yoshimura, Y. Kiyota, S. Iijima, T. Yamanaka, et al., " 0.1- mu{hbox{m}} CMOS devices using low-impurity-channel transistors (LICT) ", IEDM Tech. Dig., pp. 939-941, 1990.
2.
C. Fiegna, H. Iwai, T. Wada, T. Saito, E. Sangiorgi and B. Ricco, " A new scaling methodology for the 0.1 to 0.025- mu{hbox{m}} MOSFET ", Symp. VLSI Tech. Dig., pp. 33-34, 1993.
3.
C. Fiegna, H. Iwai, T. Wada, T. Saito, E. Sangiorgi and B. Ricco, " Scaling the MOS transistor below 0.1 mu{hbox{m}} : Methodology device structures and technology requirements ", IEEE Trans. Electron Devices, vol. 41, pp. 941-951, 1994.
4.
C. Fiegna, H. Iwai, T. Wada, T. Saito, E. Sangiorgi and B. Ricco, " Application of semiclassical device simulation to trade-off studies for sub-0.1- mu{hbox{m}} MOSFET's ", IEDM Tech. Dig., pp. 437-450, 1994.
5.
T. Ohguro, K. Yamada, N. Sugiyama, K. Usuda, Y. Akasaka, T. Yoshitomi, et al., "Tenth micron p-MOSFET's with ultrathin epitaxial channel layer grown by ultra-high-vacuum CVD", IEDM Tech. Dig., pp. 433-436, 1993.
6.
K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K. Nakajima, H. Miyamoto, et al., " 0.1- mu{hbox{m}} Delta-doped MOSFET using post low-energy implanting selective epitaxy ", Symp. VLSI Tech. Dig., pp. 19-20, 1994.
7.
T. Andoh, A. Furukawa and T. Kunio, "Design methodology for low-voltage MOSFET's", IEDM Tech. Dig., pp. 79-82, 1994.
8.
T. Ohguro, N. Sugiyama, K. Imai, K. Usuda, M. Saito, T. Yoshitomi, et al., " The influence of oxygen at epitaxial Si/Si substrate interface for 0.1- mu{hbox{m}} epitaxial Si channel n-MOSFET's grown by UHV-CVD ", Symp. VLSI Tech. Dig., pp. 21-22, 1995.
9.
H. Abiko, A. Ono, R. Ueno, S. Masuoka, S. Shishiguchi, K. Nakajima, et al., " A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15- mu{hbox{m}} ; n-n gate CMOS technology ", Symp. VLSI Tech. Dig., pp. 23-24, 1995.
10.
H. Matsuhashi, T. Ochiai, M. Kasai, T. Nakamura and S. Nishikawa, "High-performance double-layer epitaxial-channel p-MOSFET compatible with a single gate CMOSFET", Symp. VLSI Tech. Dig., pp. 36-37, 1996.
11.
K. Usuda, H. Kanaya and K. Yamada, "Scanning tunneling microscopy observation of hydrogen-terminated Si(111) surfaces at room temperature", Appl. Phys. Lett., vol. 64, pp. 3240-3242, 1994.
12.
N. Sugiyama, S. Imai and Y. Kawaguchi, "Kinetics of arsenic in silicon UHV-CVD", J. Cryst. Growth, vol. 150, pp. 994.
13.
M. Ono, M. Saito, T. Yoshitomi, C. Figna, T. Ohguro and H. Iwai, "Sub-50-nm gate length n-MOSFET's with 10-nm phosphorus source and drain junctions", IEDM Tech. Dig., pp. 119-122, 1993.
14.
J. Chung, M. C. Jeng, J. E. Moon, A. T. Wu, T. Y. chan, P. K. Ko, et al., "Deep-submicrometer MOS devices fabrication using a photoresist-ashing technique", IEEE Electron Device Lett., vol. EDL-9, pp. 186-188, 1988.