Scaling strategy for low power RF applications with multi gate oxide Dual Work function (DWF) MOSFETs utilizing self-aligned integration scheme

Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utilizing conventional CMOS platform process for the first time. Here, we obtained not only the improved transconductance (GM) and drain conductance (GD), but also the enlarged operation voltage window employing multi gate oxide structure combined with DWF gate stack. Also, the discriminative features of DWF-MOSFET operation were revealed by TCAD analysis indicating the potential ability of reduced power consumption for RF applications.

Introduction

Low power RF device technologies have been strongly required for the rapid growth of wireless and mobile products. Recently, DWF-MOSFETs have been focused to overcome the power-performance trade-off especially in analog amplifier application ([1]–[5]), because this device could realize high and low owing to the discontinuous lateral channel potential profile just under the boundary of different work-function gate materials. In spite of its advantageous device characteristics, the scaling impact of DWF-MOSFETs has not been experimentally evaluated due to the structural complexity. In this paper, we propose novel self-aligned process integration scheme to realize the DWF-MOSFET scaling down to 100 nm of with multi gate oxide structure. Finally, we discuss the impact of DWF-MOSFET performance improvement on power reduction for RF applications.