I. Introduction
Future wireless communication products require high-performance analog-to-digital converters (ADCs) that have wide signal bandwidths up to several megahertz and resolutions of more than 10 bits. However, the reduction in supply voltage that accompanies reduced transistor dimensions makes it difficult to realize high performance analog circuits. With the reduction in supply voltage, the dynamic range is also reduced. To keep the same performance, either the architecture must be changed or the thermal noise of the analog components must be reduced, which in turn will normally increase the power dissipation. Discrete-time (DT) modulators with 4 MHz bandwidth and resolutions of 11 bits have been reported [1]–[3]. Compared with DT converters, CT converters have the advantages of lower power consumption and inherent anti-aliasing filtering. Additionally, they do not suffer from noise aliasing because of the continuous-time loop filter. Moreover, the absence of stringent settling requirements enables CT converters to digitize signals up to several hundred MHz [4], which is still not possible for their DT counterparts. All these advantages result in an extended battery life and reduced system complexity, which are especially important for portable wireless devices.