Framework for HW/SW partitioning and scheduling on MPSoCs

Hardware/software (HW/SW) partitioning and scheduling are the most significant parts in co-design systems, especially in multiprocessor system-on-chip (MPSoC). It has been shown that both problems, HW/SW partitioning and HW/SW scheduling, are NP-hard. In this paper, we propose a framework for the HW/SW partitioning and scheduling. The proposed approach initially searches for typical sub-graphs in the original task graph and then reduces them to the supper nodes, in order to minimize the communication overheads. After that, the proposed algorithm schedules the tasks of the reduced task graph to the target MPSoC, according to the assigned priority to the tasks. Then, we contribute an efficient HW/SW partitioning technique to minimize the overall execution time, based on the iteratively constructing critical path and moving the tasks with the high computing cost to hardware. Simulation results show that the proposed framework in this paper is better than the existing one.

I. Introduction

Multiprocessor system-on-chips (MPSoCs) have emerged in the past decades as an important class of very large scale integration (VLSI) system. MPSoCs are widely used in networking, communications, signal processing, and multimedia among other applications [1]. The system like this consists of multiple processors, FPGAs, memories and buses. This leads to the innovation in computer architecture from simple multi-core structures with shared memory to many-core structures with distributed architecture [2].