Loading [MathJax]/extensions/MathZoom.js
Wu Jigang - IEEE Xplore Author Profile
Subscribe
ADVANCED SEARCH

Author details

< Back

Wu Jigang

Also published under: W. Jigang

Publications
28
Citations
231
Publications by Year
20042019
Co-Authors:
Show All Co-Authors (38)
Image of author Wu Jigang

Wu Jigang

Also published under: W. Jigang

Affiliation

School of Computer Science and Technology
Guangdong University of Technology
Guangzhou, P.R China

Publication Topics

Biography

Wu Jigang received the BSc degree from Lanzhou University, China in 1983, and the PhD degree from the University of Science and Technology of China in 2000. He was a research fellow at the Center for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore, from 2000 to 2009. He joined Tianjin Polytechnic University, China in 2009, as a dean, professor of the School of Computer Science and Software Engineering. His research interests include reconfigurable VLSI design, hardware/software co-design, and combinatorial search. He is a member of the IEEE.(Based on document published on 11 April 2013).
Publications
28
Citations
231
Publications by Year
20042019
Co-Authors:
Show All Co-Authors (38)
Author's Published Works

Showing 1-25 of 28 results

  • Sort

Filter Results

Show

Sort By

Results

Task Scheduling in Mobile Edge Computing with Stochastic Requests and M/M/1 Servers

Luo Yuchong;Wu Jigang;Wu Yalan;Chen Long

2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)
Year: 2019 | Conference Paper |
Cited by: Papers (15)
A multi-user mobile edge computing system with stochastic requests and M/M/1 queuing based servers is proposed in this paper. The problem of minimizing the total response time of all tasks is formulated, which is proved to be NP-complete. A greedy algorithm is proposed to solve the mentioned optimization problem, which prefers to assign task to the server with minimum response time for the task. S...Show More

Task Scheduling in Mobile Edge Computing with Stochastic Requests and M/M/1 Servers

Luo Yuchong;Wu Jigang;Wu Yalan;Chen Long

Year: 2019 | Conference Paper |

Constructing Sub-Arrays with ShortInterconnects from Degradable VLSI Arrays

Wu Jigang;Thambipillai Srikanthan;Guiyuan Jiang;Kai Wang

IEEE Transactions on Parallel and Distributed Systems
Year: 2014 | Volume: 25, Issue: 4 | Journal Article |
Cited by: Papers (25)
Reducing the interconnection length of VLSI arrays leads to less capacitance, power dissipation and dynamic communication cost between the processing elements (PEs). This paper develops efficient algorithms for constructing tightly-coupled subarrays from the mesh-connected VLSI arrays with faulty PEs. For a given size $r\cdot s$ of the target (logical) array, the proposed algorithm searches and re...Show More

Constructing Sub-Arrays with ShortInterconnects from Degradable VLSI Arrays

Wu Jigang;Thambipillai Srikanthan;Guiyuan Jiang;Kai Wang

Year: 2014 | Volume: 25, Issue: 4 | Journal Article |

Algorithm for Communication Synchronization on Reconfigurable Processor Arrays with Faults

Wu Jigang;Guiyuan Jiang;Yuanrui Zhang;Yuanbo Zhu

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
Year: 2012 | Conference Paper |
Cited by: Papers (1)
Efficient fault tolerant techniques for reconfigurable multiprocessor array have been extensively studied to construct maximum target array from host array with faulty processors. Existing work focused on the reconfiguration algorithm without considering the communication synchronization of the target array. This paper proposes an algorithm to rearrange the long interconnects of the target array, ...Show More

Algorithm for Communication Synchronization on Reconfigurable Processor Arrays with Faults

Wu Jigang;Guiyuan Jiang;Yuanrui Zhang;Yuanbo Zhu

Year: 2012 | Conference Paper |

Efficient Reconfiguration Algorithm for Three-dimensional VLSI Arrays

Guiyuan Jiang;Wu Jigang;Jizhou Sun

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
Year: 2012 | Conference Paper |
Cited by: Papers (4)
Reconfigurable VLSI array is a well known fault tolerant architecture for parallel computing, but few reconfiguration approaches are reported so far for three-dimensional (3D) arrays due to the high complexity of reconfiguration. This paper is devoted to develop reconfiguration algorithm for three-dimensional degradable VLSI arrays. Three bypass schemes and three rerouting schemes are proposed to ...Show More

Efficient Reconfiguration Algorithm for Three-dimensional VLSI Arrays

Guiyuan Jiang;Wu Jigang;Jizhou Sun

Year: 2012 | Conference Paper |

Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms

Samarth Kaushik;Amit Kumar Singh;Wu Jigang;Thambipillai Srikanthan

2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming
Year: 2011 | Conference Paper |
Cited by: Papers (9)
The rapid increase in the complexity of real-life applications has led to the perpetual demand of refined architectural designs. Multiprocessor systems-on-chip (MPSoC) emerges as one of the possible solution for satiating such enormous computational needs. These MPSoCs are employed with Network-On-Chip (NoC) interconnect for power efficient and scalable inter-communication required between process...Show More

Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms

Samarth Kaushik;Amit Kumar Singh;Wu Jigang;Thambipillai Srikanthan

Year: 2011 | Conference Paper |

Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management

Amit Kumar Singh;Akash Kumar;Wu Jigang;Thambipillai Srikanthan

2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming
Year: 2011 | Conference Paper |
Real-time multi-media applications are increasingly mapped on modern embedded systems based on Multiprocessor Systems-on-Chip (MPSoCs). Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisfy their performance constraints. Exploring all the mappings, i.e. tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is...Show More

Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management

Amit Kumar Singh;Akash Kumar;Wu Jigang;Thambipillai Srikanthan

Year: 2011 | Conference Paper |

Sliding Mode Control Algorithm Design for a Class of Unmatched Uncertain System

Zhao Zhanshan;Zhang Jing;Wu Jigang;Wang Yongji

2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming
Year: 2011 | Conference Paper |
An Integral sliding mode control algorithm for a class of unmatched uncertain system is proposed in this paper. In order to make that the perturbation is minimal, the perturbation is provided into two parts by projection matrix--the matched and unmatched perturbation. It is also shown that when the minimum is attained and the resulting perturbation is not amplified. The controller design uses inte...Show More

Sliding Mode Control Algorithm Design for a Class of Unmatched Uncertain System

Zhao Zhanshan;Zhang Jing;Wu Jigang;Wang Yongji

Year: 2011 | Conference Paper |

A Performance Evaluation of Cellular/WLAN Integrated Networks

Liying Yang;Guozhi Song;Wu Jigang

2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming
Year: 2011 | Conference Paper |
Cited by: Papers (1) | Patents (8)
One of the key issues in cellular networks is the traffic load imbalance problem in the form of hot-spots caused by the different user mobility levels. A sound approach to address the problem currently is the integration of different heterogeneous networks, such as constructing a system via connecting cellular network and wireless local area network (WLAN) seamlessly. In general, the traffic volum...Show More

A Performance Evaluation of Cellular/WLAN Integrated Networks

Liying Yang;Guozhi Song;Wu Jigang

Year: 2011 | Conference Paper |

New upper bound of target array for reconfigurable VLSI arrays

Wu Jigang;Xiaogang Han

2011 IEEE International Conference of Electron Devices and Solid-State Circuits
Year: 2011 | Conference Paper |
Reconfiguring a VLSI array with faults is to construct a maximum logical sub-array (target array). A large target array implies a good harvest of the corresponding reconfiguration algorithm. Thus, a tight upper bound of the harvest can be directly used to evaluate the performance of the reconfiguration algorithm. This paper presents a new approach to calculate the upper bound of the harvest for th...Show More

New upper bound of target array for reconfigurable VLSI arrays

Wu Jigang;Xiaogang Han

Year: 2011 | Conference Paper |

Framework for HW/SW partitioning and scheduling on MPSoCs

Honglei Han;Liu Wenju;Wu Jigang;Li Hui

2010 International Conference on Computer and Information Application
Year: 2010 | Conference Paper |
Cited by: Papers (1)
Hardware/software (HW/SW) partitioning and scheduling are the most significant parts in co-design systems, especially in multiprocessor system-on-chip (MPSoC). It has been shown that both problems, HW/SW partitioning and HW/SW scheduling, are NP-hard. In this paper, we propose a framework for the HW/SW partitioning and scheduling. The proposed approach initially searches for typical sub-graphs in ...Show More

Framework for HW/SW partitioning and scheduling on MPSoCs

Honglei Han;Liu Wenju;Wu Jigang;Li Hui

Year: 2010 | Conference Paper |

Practical algorithm for shortest path on transportation network

Zhen Zhang;Wu Jigang;Xinming Duan

2010 International Conference on Computer and Information Application
Year: 2010 | Conference Paper |
Cited by: Papers (4)
The shortest path problem is to find a path between two vertices (nodes) on a given graph, such that the sum of the weights on its constituent edges is minimized. This problem has been intensively investigated over years, due to its extensive applications in graph theory, artificial intelligence, computer network and the design of transportation systems. The classic Dijkstra's algorithm was design...Show More

Practical algorithm for shortest path on transportation network

Zhen Zhang;Wu Jigang;Xinming Duan

Year: 2010 | Conference Paper |

Accelerating Reconfiguration for Degradable Mesh-Connected Processor Arrays

Jing Wang;Wu Jigang;Yuanrui Zhang;Dakun Zhang

2010 3rd International Symposium on Parallel Architectures, Algorithms and Programming
Year: 2010 | Conference Paper |
Cited by: Papers (2)
This paper proposes a fast reconfiguration algorithm for the two-dimensional degradable mesh-connected processor arrays. The proposed algorithm simplifies a dynamic programming approach to construct logical columns. For each processing element lying in the logical columns, the calculation is reduced from five operations (one assignment, two additions and two comparisons) that are taken in the stat...Show More

Accelerating Reconfiguration for Degradable Mesh-Connected Processor Arrays

Jing Wang;Wu Jigang;Yuanrui Zhang;Dakun Zhang

Year: 2010 | Conference Paper |

A Novel Approach for Multilevel Fixed Outline Floorplanning

Baofang Chang;Wu Jigang;Thambipillai Srikanthan;Lian Li

2010 3rd International Symposium on Parallel Architectures, Algorithms and Programming
Year: 2010 | Conference Paper |
Multilevel strategy is one of the most popular methods for fixed outline floor planning. It partitions an original circuit into some sub-circuits and then merges them into relatively big ones. In this paper, we propose a novel evaluation approach and integrate it into the simulated annealing framework in the merging stage. Moreover, a novel search technique, which can almost keep away from the loc...Show More

A Novel Approach for Multilevel Fixed Outline Floorplanning

Baofang Chang;Wu Jigang;Thambipillai Srikanthan;Lian Li

Year: 2010 | Conference Paper |

Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays

Wu Jigang;Thambipillai Srikanthan;Xiaogang Han

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year: 2010 | Volume: 18, Issue: 2 | Journal Article |
Cited by: Papers (25)
This paper presents novel techniques to accelerate the reconfiguration of degradable very large scale integration arrays. A preprocessing step is used to derive the upper and lower size bounds of the maximum logical array (MLA) such that only those subarrays that possibly contain the MLA are reconfigured, thereby reducing the reconfiguration time and also obtaining a same-sized logical array. In a...Show More

Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays

Wu Jigang;Thambipillai Srikanthan;Xiaogang Han

Year: 2010 | Volume: 18, Issue: 2 | Journal Article |

Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms

Amit Kumar Singh;Wu Jigang;Alok Prakash;Thambipillai Srikanthan

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Year: 2009 | Conference Paper |
Cited by: Papers (19)
Mapping of applications onto multiprocessor system-on-chip (MPSoC) can be realized either at design-time or run-time. At any time the number of tasks executing in MPSoC platform can exceed the available resources, requiring efficient run-time mapping techniques to meet the real-time constraints of the applications. This paper presents two run-time mapping heuristics for mapping the tasks of an app...Show More

Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms

Amit Kumar Singh;Wu Jigang;Alok Prakash;Thambipillai Srikanthan

Year: 2009 | Conference Paper |

A Hybrid Branch-and-Bound Strategy for Hardware/Software Partitioning

Wu Jigang;Baofang Chang;Thambipillai Srikanthan

2009 Eighth IEEE/ACIS International Conference on Computer and Information Science
Year: 2009 | Conference Paper |
This paper proposes a hybrid branch and bound strategy based on global best-first (GBF) scheme and local best-first (LBF) scheme.The proposed hybrid approach not only inherits the merit of GBF that produces fewer expanded nodes but also significantly reduces the search space of GBF, and thus it efficiently overcomes the blind search of the LBF scheme. A new data structure called string-queue is al...Show More

A Hybrid Branch-and-Bound Strategy for Hardware/Software Partitioning

Wu Jigang;Baofang Chang;Thambipillai Srikanthan

Year: 2009 | Conference Paper |

Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection

Tao Li;Wu Jigang;Siew-Kei Lam;Thambipillai Srikanthan;Xicheng Lu

2009 Eighth IEEE/ACIS International Conference on Computer and Information Science
Year: 2009 | Conference Paper |
Cited by: Papers (5)
Custom-instruction selection is an essential phase in custom-instruction generation. It determines the most profitable custom instruction candidates for hardware implementation. In this paper, a practical computing model is proposed for the problem of custom-instruction selection that takes into account the hardware area constraint. Based on the new computing model, a novel heuristic algorithm is ...Show More

Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection

Tao Li;Wu Jigang;Siew-Kei Lam;Thambipillai Srikanthan;Xicheng Lu

Year: 2009 | Conference Paper |

Efficient Approximate Algorithm for Hardware/Software Partitioning

Wu Jigang;Ting Lei;Thambipillai Srikanthan

2009 Eighth IEEE/ACIS International Conference on Computer and Information Science
Year: 2009 | Conference Paper |
Hardware/software (HW/SW) partitioning is one of the crucial steps of co-design systems. It determines which components of the systems are implemented in hardware and which ones are in software. In this paper the computing model is extended to cater for the path-based HW/SW partitioning with the fine granularity in which communication penalties between system components must be considered. On the ...Show More

Efficient Approximate Algorithm for Hardware/Software Partitioning

Wu Jigang;Ting Lei;Thambipillai Srikanthan

Year: 2009 | Conference Paper |

Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms

Amit Kumar Singh;Wu Jigang;Alok Prakash;Thambipillai Srikanthan

2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Year: 2009 | Conference Paper |
Cited by: Papers (16)
The number of tasks executing in MPSoC platform can exceed the available resources, requiring efficient run-time mapping strategies to meet the real-time constraints of the applications. This paper describes two new run-time mapping heuristics for mapping applications onto NoC-based heterogeneous multiprocessor systems-on-chip (MPSoC). The heuristics proposed in this paper attempt to map the tasks...Show More

Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms

Amit Kumar Singh;Wu Jigang;Alok Prakash;Thambipillai Srikanthan

Year: 2009 | Conference Paper |

Performance Estimation: IPC

Abhijit Ray;Wu Jigang;Thambipillai Srikanthan

2008 The 9th International Conference for Young Computer Scientists
Year: 2008 | Conference Paper |
Cited by: Papers (1)
Performance estimation of a processor can easily lead to a large saving in time, which would otherwise be spent on time consuming simulations. Poor choice of processor can lead to an expensive design due to either the choice of an expensive processor or due to a large hardware as the selected processor severely under performs. In this work, we estimate the IPC (instructions per cycle) of the proce...Show More

Performance Estimation: IPC

Abhijit Ray;Wu Jigang;Thambipillai Srikanthan

Year: 2008 | Conference Paper |

Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors

Xiongfei Liao;Wu Jigang;Thambipillai Srikanthan

2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)
Year: 2007 | Conference Paper |
Cited by: Papers (1)
This paper explores the thermal problems in future CMPs in multiprogrammed environment for heat balancing. We first give the observation of the temperature variation of cores in this scenario. Then we propose a temperature-aware submesh allocation scheme to manage cores with submeshes and allocate submeshes of cores to jobs under temperature-aware policies to balance heat chip-wide. Several schedu...Show More

Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors

Xiongfei Liao;Wu Jigang;Thambipillai Srikanthan

Year: 2007 | Conference Paper |

Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

Wu Jigang;Thambipillai Srikanthan;Xiaodong Wang

IEEE Transactions on Computers
Year: 2007 | Volume: 56, Issue: 10 | Journal Article |
Cited by: Papers (38)
This paper deals with the issue of developing efficient algorithms for reconfiguring two-dimensional VLSI arrays linked by 4-port switches in the presence of faulty processing elements (PEs). The proposed algorithm reroutes the arrays with faults in both row and column directions at the same time. Unlike previous work, the compensation technique to replace the faulty PE is not restricted to the ad...Show More

Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches

Wu Jigang;Thambipillai Srikanthan;Xiaodong Wang

Year: 2007 | Volume: 56, Issue: 10 | Journal Article |

One-dimensional Search Algorithms for Hardware/Software Partitioning

Wu Jigang;Thambipillai Srikanthan;Guang Chen

2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)
Year: 2007 | Conference Paper |
Cited by: Papers (1)
Hardware/software (HW/SW) partitioning is one of the key challenges in HW/SW co-design. This paper presents a new formulation to handle the HW/SW partitioning problem, which has been proved to be NP-hard. The proposed formulation transforms the partitioning problem into an extended 0-1 knapsack problem that is approximately solved in this paper by scanning a one-dimensional search space, instead o...Show More

One-dimensional Search Algorithms for Hardware/Software Partitioning

Wu Jigang;Thambipillai Srikanthan;Guang Chen

Year: 2007 | Conference Paper |

New Reconfiguration Algorithm for Degradable VLSI Arrays

Wu Jigang;Thambipillai Srikanthan;Xiaodong Wang

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Year: 2006 | Conference Paper |
A new rerouting approach is proposed in this paper for the reconfiguration of two-dimensional degradable VLSI arrays under the constraint of row and column rerouting. The proposed approach chooses the local best processing element in each step to construct the leftmost logical columns, in order to utilize as many non-faults lying in the excluded rows as possible to enlarge the harvest of the algor...Show More

New Reconfiguration Algorithm for Degradable VLSI Arrays

Wu Jigang;Thambipillai Srikanthan;Xiaodong Wang

Year: 2006 | Conference Paper |

Efficient Algorithms for Hardware/Software Partitioning to Minimize Hardware Area

Wu Jigang;Thambipillai Srikanthan

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Year: 2006 | Conference Paper |
Cited by: Papers (3)
Area efficiency is one of the major considerations in constraint aware hardware/software partitioning process. This paper models hardware/software partitioning as an optimization problem with the objective of minimizing area utilization under the constraints of execution time and power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the method solving t...Show More

Efficient Algorithms for Hardware/Software Partitioning to Minimize Hardware Area

Wu Jigang;Thambipillai Srikanthan

Year: 2006 | Conference Paper |

IEEE Account

Purchase Details

Profile Information

Need Help?

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.