I. INTRODUCTION
THE DOUBLE-GATE (DG) MOSFET is one of the most promising architectures for scaling CMOS devices down to nanometre size, since they allow a considerable reduction of the short-channel effects (SCEs), such as threshold voltage roll-off, drain-induced barrier lowering (DIBL), and subthreshold slope degradation, compared to planar single-gate MOSFETs. DG MOSFET exhibits almost ideal sub-threshold swing (60mv/dec), lower output conductance and higher drive current. Moreover, in DG MOSFETs, the channel material is preferred to be undoped as absence of dopant atoms in the channel material eliminates adverse effects, such as mobility degradation and random microscopic fluctuations of dopant atoms, which can lead to unwanted dispersion in the device characteristics. The use of high dielectric become prominent in further scaling down the MOSFET as well as improving the performance.