Energy and delay-aware mapping for real-time digital processing system on network on chip platforms

The mapping algorithm is one of the most important topics for Network on chip design. This paper proposes a new mapping algorithm, which uses an optimized energy model. In addition, we adopt a multiple-to-multiple mapping scheme to enhance concurrency and increase efficiency. The proposed approach uses NSGA-II to achieve the global optimal solutions for NoC platforms. The simulation results prove that the proposed approach can achieve better energy and delay performance for both 2-D and 3-D NoC than random mapping.