A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS | IEEE Conference Publication | IEEE Xplore

A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS


Abstract:

This paper presents a digital-intensive RF sampling receiver composed of a noise-canceling bandpass low-noise amplifier (LNA) and an RF analog-to-digital converter (ADC) ...Show More

Abstract:

This paper presents a digital-intensive RF sampling receiver composed of a noise-canceling bandpass low-noise amplifier (LNA) and an RF analog-to-digital converter (ADC) for multi-band multi-mode wireless communication. The proposed LNA employs an on-chip transformer to combine the outputs of a common-gate and a common-source LNA to reduce the noise figure and enhance the linearity, while providing tunable bandpass filtering from 1.8 to 2.4-GHz. The RF ADC employs a time-based architecture that uses time-interleaved VCOs with 1st order noise shaping property, which benefits from enhanced time resolution of advanced CMOS process. A prototype chip implemented in 90 nm CMOS process has an area of 0.3 mm2 and achieves SNR of 50 dB for 1-MHz signal bandwidth at 1.8 to 2.4-GHz carrier frequency, while consuming 20 mW from 1.2 V supply.
Date of Conference: 23-25 May 2010
Date Added to IEEE Xplore: 03 June 2010
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Conference Location: Anaheim, CA, USA
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I. Introduction

The rapid increase in the number of communication standards has intensified the research effort for a multi-band multimode wireless receiver. Employing a high-performance ADC near the antenna has been considered an attractive architecture for multi-band multi-mode wireless communication, since it can take advantage of signal processing power and reconfigurability of DSPs. Unfortunately, designing a high performance ADC at radio frequency (RF) is not an easy task. Although there have been several attempts for direct RF sampling bandpass ADCs at GHz range [1], [2], [3], their power consumption and area are very large due to the high speed DACs and Gm-LC filters that use multiple on-chip spiral inductors. Moreover, frequency range of the ADC is very limited as the stability of the ADC is highly sensitive to coefficients of the loop, thus making them unsuitable for multi-band applications. While a time-based ADC employing time-interleaved VCOs [4] requires an antialias bandpass filter at its input, it is a promising architecture for multi-band multi-mode applications as it consumes lowpower, small area and has widely tunable frequency without suffering from any stability issue.

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1.
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2.
J. Ryckaert, J. Borremans, B. Verbruggen, L. Bos, C. Armiento, J. Cran-inckx, et al., "A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS", IEEE J. Solid-State Circuits, vol. 44, pp. 2873-2880, Nov. 2009.
3.
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4.
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5.
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6.
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7.
W.-H. Chen, G. Liu, B. Zdravko and A. M. Niknejad, "A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation", IEEE J. Solid-State Circuits, vol. 43, pp. 1164-1176, May 2008.
8.
Y.-G. Yoon, J. Kim, T.-K. Jang and S. H. Cho, "A time-based bandpass ADC using time-interleaved voltage-controlled oscillators", IEEE Trans. Circuits Syst. I, vol. 55, pp. 3571-3581, Dec. 2008.
9.
D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, et al., "A 5-GHz Fully Integrated ESD-Protected Low-Noise Amplifier in 90-nm RF CMOS", IEEE 1. Solid-State Circuits, vol. 40, pp. 1434-1442, July 2005.
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References

References is not available for this document.