Design of a generic network on chip frame work for store & forward routing for 2D mesh topology

The need of high performing, mega functionality solutions are becoming important day by day. The implementation of these mega functional modules which was done using common bus architecture, parallel bus architecture, pipelining are becoming ineffective and posing a bottleneck in terms of performance and throughput in this billion transistor era. To overcome these performance issues, a new paradigm in interconnect technology was proposed. The idea was to implant the concept of data transfer in data communication networks into silicon thus providing advantages of low power scalable high performing architecture with a small increase in die area for routing resources. This paper discusses the design of a generic frame work for network on chip based systems using store and forward strategy.

1. Introduction

In traditional systems the modules are interconnected by the common bus. This technique ruled for many decades but have a serious disadvantage in terms of performance in high performing circuits because of transmission delays between the modules. The modules have to poll or arbitrate for the bus for transmitting data from one module to another. In this case only two modules connected to the bus can communicate with each other while leaving others idle.