Abstract:
Results are presented from work aimed at demonstrating the feasibility of Plasma Doping (PLAD) to fabricate P+ source/drain regions for 0.25-0.3μm buried channel PMOSFETS...Show MoreMetadata
Abstract:
Results are presented from work aimed at demonstrating the feasibility of Plasma Doping (PLAD) to fabricate P+ source/drain regions for 0.25-0.3μm buried channel PMOSFETS for the first time. Device characteristics are compared between PLAD and conventionally-formed source/drain junctions using ion implantation of Boron and BF2 at energies of 2,5, and 10 keV Superior threshold voltage roll-off, off-current leakage, and high punch-through resistance are obtained for PLAD MOSFETs processed at pulsed negative voltage of 3.5 kV applied to the wafer with a BF3 source gas used to implant boron ions. The process capability of PLAD is examined by looking at sheet resistance uniformity and junction leakage. Plasma Doping is shown to be a viable alternative to ion implantation for the fabrication of next generation deep sub-half micron devices with the potential for significantly reduced cost.
Date of Conference: 09-11 September 1996
Date Added to IEEE Xplore: 22 March 2010
Print ISBN:286332196X
Conference Location: Bologna, Italy
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