Plasma Doped (PLAD) Deep Sub-Half Micron Buried Channel PMOSFETS and its Application to Next Generation ULSI Circuits

Results are presented from work aimed at demonstrating the feasibility of Plasma Doping (PLAD) to fabricate P⁺ source/drain regions for 0.25-0.3μm buried channel PMOSFETS for the first time. Device characteristics are compared between PLAD and conventionally-formed source/drain junctions using ion implantation of Boron and BF₂ at energies of 2,5, and 10 keV Superior threshold voltage roll-off, off-current leakage, and high punch-through resistance are obtained for PLAD MOSFETs processed at pulsed negative voltage of 3.5 kV applied to the wafer with a BF₃ source gas used to implant boron ions. The process capability of PLAD is examined by looking at sheet resistance uniformity and junction leakage. Plasma Doping is shown to be a viable alternative to ion implantation for the fabrication of next generation deep sub-half micron devices with the potential for significantly reduced cost.