Design of a Generic Network on Chip Frame Work Using Wormhole Routing for 2D Mesh

The requirements of high performance mega functional solutions are becoming important day by day. With the advancement in semiconductor devices and fabrication technology, it is possible to pack more logic in smaller area of silicon. But the implementation of these mega functional modules using common bus architecture, parallel bus architecture, pipelining are becoming ineffective and posing a bottleneck in terms of performance and throughput in this billion transistor era. To overcome these performance issues, a new paradigm in interconnect technology was proposed. The proposal is to implant the concept of data transfer in data communication networks providing advantages of low power scalable high performance architecture. This can be achieved with a small increase in silicon area, for routing resources. This paper discusses the design of a generic frame work for wormhole routing strategy for 2D mesh topology. It also discusses the data transfer operation and other aspects of this frame work.

I. INTRODUCTION

The idea of implanting network solutions on silicon is becoming a promising solution for high performance, scalable architecture. This novel idea interconnects the different modules using topologies like 2D mesh, torus etc instead of a common bus. The inter process communication among different modules takes place by transfer of packets instead of polling or arbitration as in bus architecture. The operations of Network-on-Chip are assisted by three routing strategies namely store-and-forward, virtual cut-through, wormhole routing which specifies the method on how the router at intermediate nodes processes the packets and forwards to the next node towards the destination. Several routing algorithms in both adaptive and non adaptive are proposed in this area. This paper starts discussion with the design of the generic frame work for wormhole routing strategy using dimensional XY routing. Wormhole routing is a special case of cut-through switching. Instead of storing a packet completely in a node and then transmitting it to the next node, wormhole routing operates by advancing the head of a packet directly from incoming to outgoing channels of the routing chip. A packet is divided into a number of flits (flow control digits) for transmission. The size of a flit depends on system parameters, in particular, the channel width. The header flit (or flits) governs the route. As soon as a node examines the header flit(s) of a message, it selects the next channel on the route and begins forwarding flits down that channel. As the header advances along the specified route, the remaining flits follow in a pipeline fashion. The flits travel along the X direction and then take the Y direction to reach the destination. Because most flits contain no routing information, the flits in a message must remain in contiguous channels of the network and cannot be interleaved with the flits of other messages. When the header flit of a message is blocked, all of the flits of a message stop advancing and block the progress of any other message requiring the channels they occupy. Wormhole routing avoids memory bandwidth in the nodes through which messages are routed. Only a small FIFO flit buffer can be used. It also makes the network latency largely insensitive to path length. On the other hand, in order to reduce the effect of message blocking, physical channels may be split into virtual channels and these will be used to increase the total throughput of the physical channel. Virtual channels are logical entities associated with a physical link used to distinguish multiple data streams traversing the same physical channel. They are multiplexed over a physical channel in a demand-driven manner, with bandwidth allocated to each virtual channel as needed.