Abstract:
A simple four-quadrant analog BiCMOS multiplier that operates with /spl plusmn/0.75 V supplies is presented. The circuit uses multiple-input floating-gate transistors and...Show MoreMetadata
Abstract:
A simple four-quadrant analog BiCMOS multiplier that operates with /spl plusmn/0.75 V supplies is presented. The circuit uses multiple-input floating-gate transistors and is based on a folded Gilbert multiplier structure. It has 1 V/sub pp/ input-output signal swing and less than 1% THD over the specified range. SPICE simulations verify the operation of the circuit.
Published in: 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96
Date of Conference: 15-15 May 1996
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-3073-0
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Cites in Papers - IEEE (4)
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1.
S. Vlassis, S. Siskos, "Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51, no.2, pp.329-341, 2004.
2.
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3.
P. Hasler, B.A. Minch, C. Diorio, "Adaptive circuits using pFET floating-gate devices", Proceedings 20th Anniversary Conference on Advanced Research in VLSI, pp.215-229, 1999.
4.
J. Ramirez-Angulo, G. Gonzalez-Altamirano, S.C. Choi, "Modeling multiple-input floating-gate transistors for analog signal processing", 1997 IEEE International Symposium on Circuits and Systems (ISCAS), vol.3, pp.2020-2023 vol.3, 1997.
