Flexible FPGA-DSP solution for an IR-UWB testbed

A flexible solution for hardware implementation of an IR-UWB testbed processing unit is presented on this paper. The FPGA-DSP hybrid architecture satisfies the reconfigurability requirements of a testbed and provides enough processing power needed for an UWB communication. The proposed solution has been used to implement an UWB testbed for ranging and low data rate communications that complies with regulations of European Union for UWB communication.

I. Introduction

Ultra-Wideband (UWB) systems as defined by Federal Communications Commission (FCC) are any communication system based on a signal with a fractional bandwidth greater than 20% or with a bandwidth greater than 500 MHz. This definition includes both carrier-based systems as well as impulse radio (IR) systems. In 2002, the FCC published a regulatory report allowing UWB signal transmission with radiated power spectral density (PSD) below -41.3 dBm/MHz in the 3.1GHz-10.6GHz frequency range. Recently, the European Commission (EC) has released the indoor UWB emission spectral mask for the member states of the European Union, allowing a PSD up to -41.3 dBm/MHz in the 6.0GHz-8.5GHz frequency range [7] [9].