Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays

This paper presents novel techniques to accelerate the reconfiguration of degradable very large scale integration arrays. A preprocessing step is used to derive the upper and lower size bounds of the maximum logical array (MLA) such that only those subarrays that possibly contain the MLA are reconfigured, thereby reducing the reconfiguration time and also obtaining a same-sized logical array. In addition, the partial rerouting approach is generalized so that as many as possible previous routing results can be reused in the current rerouting step. The reconfiguration time is reduced from $ O((1-\rho)\cdot \beta \cdot m \cdot n)$ to its lower bound $ O((1-\rho)\cdot m\cdot n)$ for $ m\times n$ host arrays with small fault density $ \rho $, where $ \beta $ is the expected routing length required per logical column.

I. Introduction

With the advanced techniques in very large scale integration arrays (VLSI), a huge number of processing elements (PEs) are able to be built on a single chip. Thus, fault-tolerant techniques must be required to maintain dependability in systems on use. The high regularity of VLSI arrays allows fault tolerance through reconfiguration. One reconfiguration method is called redundancy approach, and the other is called degradation approach [1], [2]. In degradation approach, an algorithm, namely Gcr, was proposed in [3] to find a maximal logical array (MLA) that contains a set of the selected rows. The techniques performing row-exclusion and compensation were proposed and combined with Gcr into a heuristic algorithm, namely Rcrt00, to generate an approximate MLA [4]. Recently, the power dissipation of a logical array was reduced in [5] and novel algorithms for MLA were presented in [6] and [7].