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Flexible LDPC Decoder Design for Multigigabit-per-Second Applications


Abstract:

Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. Howev...Show More

Abstract:

Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. However, the efficient implementation of high-throughput LDPC decoders adaptable for various channel conditions still remains challenging. In this paper, a low-complexity reconfigurable VLSI architecture for high-speed LDPC decoders is presented. Shift-LDPC codes are incorporated within the design and have shown not only comparable decoding performance to computer-generated random codes but also high hardware efficiency in high-speed applications. The single-minimum Min-Sum decoding scheme and the nonuniform quantization scheme are explored to reduce the complexity of computing core and the memory requirement. The well-known Benes network is employed to construct the configurable permutation network to support multiple shift-LDPC codes with various code parameters. The ASIC implementation results of an (8192, 7168) (4, 32)-regular shift-LDPC decoder demonstrate a maximum decoding throughput of 3.6 Gbits/s at 16 iterations, which outperforms the state-of-the-art design for high-speed flexible LDPC decoders by many times with even less hardware.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 57, Issue: 1, January 2010)
Page(s): 116 - 124
Date of Publication: 24 March 2009

ISSN Information:


I. Introduction

Low-density parity-check (LDPC) codes, which were originally introduced by Gallager in his Ph.D. dissertation in the early 1960s [1], have been ignored for a long time for the requirement of high-complexity computation. Since their rediscovery by MacKay and Neal [2], [3], LDPC codes have become one of the most attractive topics of interest in both academia and industry. Compared with turbo codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near-Shannon-limit error-correcting capacity, low error floor, reasonable implementation complexity, as well as high intrinsic degrees of parallelism. With these remarkable characteristics, LDPC codes have been recently adopted in several industrial standards such as wireless local area networks (IEEE 802.11n) [4], wireless metropolitan area networks (IEEE 802.16e) [5], China's Digital Television Terrestrial Broadcasting standards (DTTB) [6], and Digital Video Broadcasting-Satellite-Second Generation (DVB-S2) [7].

References

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