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Flexible LDPC Decoder Design for Multigigabit-per-Second Applications


Abstract:

Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. Howev...Show More

Abstract:

Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. However, the efficient implementation of high-throughput LDPC decoders adaptable for various channel conditions still remains challenging. In this paper, a low-complexity reconfigurable VLSI architecture for high-speed LDPC decoders is presented. Shift-LDPC codes are incorporated within the design and have shown not only comparable decoding performance to computer-generated random codes but also high hardware efficiency in high-speed applications. The single-minimum Min-Sum decoding scheme and the nonuniform quantization scheme are explored to reduce the complexity of computing core and the memory requirement. The well-known Benes network is employed to construct the configurable permutation network to support multiple shift-LDPC codes with various code parameters. The ASIC implementation results of an (8192, 7168) (4, 32)-regular shift-LDPC decoder demonstrate a maximum decoding throughput of 3.6 Gbits/s at 16 iterations, which outperforms the state-of-the-art design for high-speed flexible LDPC decoders by many times with even less hardware.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 57, Issue: 1, January 2010)
Page(s): 116 - 124
Date of Publication: 24 March 2009

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I. Introduction

Low-density parity-check (LDPC) codes, which were originally introduced by Gallager in his Ph.D. dissertation in the early 1960s [1], have been ignored for a long time for the requirement of high-complexity computation. Since their rediscovery by MacKay and Neal [2], [3], LDPC codes have become one of the most attractive topics of interest in both academia and industry. Compared with turbo codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near-Shannon-limit error-correcting capacity, low error floor, reasonable implementation complexity, as well as high intrinsic degrees of parallelism. With these remarkable characteristics, LDPC codes have been recently adopted in several industrial standards such as wireless local area networks (IEEE 802.11n) [4], wireless metropolitan area networks (IEEE 802.16e) [5], China's Digital Television Terrestrial Broadcasting standards (DTTB) [6], and Digital Video Broadcasting-Satellite-Second Generation (DVB-S2) [7].

Cites in Papers - |

Cites in Papers - IEEE (26)

Select All
1.
Jakub Hyla, Wojciech Sułek, "Short Blocklength Nonbinary Raptor-Like LDPC Coding Systems Design and Simulation", IEEE Access, vol.13, pp.3849-3863, 2025.
2.
Daniel B. Dermont, Jérémy Nadal, François Leduc-Primeau, "Single-Minimum LDPC Decoding Offset Optimization Methods", 2022 17th Canadian Workshop on Information Theory (CWIT), pp.21-26, 2022.
3.
Homayoon Hatami, David G. M. Mitchell, Daniel J. Costello, Thomas E. Fuja, "A Threshold-Based Min-Sum Algorithm to Lower the Error Floors of Quantized LDPC Decoders", IEEE Transactions on Communications, vol.68, no.4, pp.2005-2015, 2020.
4.
Homayoon Hatami, David G. M. Mitchell, Daniel J. Costello, Thomas Fuja, "A Modified Min-Sum Algorithm for Quantized LDPC Decoders", 2019 IEEE International Symposium on Information Theory (ISIT), pp.2434-2438, 2019.
5.
Chao Yang, Shusen Jing, Xiao Liang, Zaichen Zhang, Xiaohu You, Chuan Zhang, "A LARGE-SCALE EXTENSION OF SPARSE-CODE MULTIPLE-ACCESS SYSTEM", 2018 IEEE Global Conference on Signal and Information Processing (GlobalSIP), pp.848-852, 2018.
6.
Jiejun Jin, Xiao Liang, Yunhao Xu, Zaichen Zhang, Xiaohu You, Chuan Zhang, "LDPC Decoder Based on Markov Chain Monte Carlo Method", 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.219-222, 2018.
7.
Kai Sun, Yifei Shen, Yingjie Lao, Zaichen Zhang, Xiaohu You, Chuan Zhang, "A New Error Correction Scheme for Physical Unclonable Function", 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.374-377, 2018.
8.
Xingchi Zhang, Lulu Ge, Xiaohu You, Chuan Zhang, "Synthesizing LDPC Belief Propagation Decoding with Molecular Reactions", 2018 IEEE International Conference on Communications (ICC), pp.1-6, 2018.
9.
Feng Yi, Zaichen Zhang, Xiaohu You, Chuan Zhang, "Efficient Circulant Matrix Construction and Implementation for Compressed Sensing", 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp.1174-1178, 2018.
10.
Huan Li, Jing Guo, Chen Guo, Donglin Wang, "A low-complexity min-sum decoding algorithm for LDPC codes", 2017 IEEE 17th International Conference on Communication Technology (ICCT), pp.102-105, 2017.
11.
Chuan Zhang, Yuan-Hao Huang, Farhana Sheikh, Zhongfeng Wang, "Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.7, no.4, pp.477-490, 2017.
12.
Shusen Jing, Junmei Yang, Zhongfeng Wang, Xiaohu You, Chuan Zhang, "Algorithm and architecture for joint detection and decoding for MIMO with LDPC codes", 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-4, 2017.
13.
Peter Hailes, Lei Xu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo, "A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder", IEEE Access, vol.5, pp.20965-20984, 2017.
14.
Oana Boncalo, "QC-LDPC Gear-Like Decoder Architecture with Multi-domain Quantization", 2016 Euromicro Conference on Digital System Design (DSD), pp.244-251, 2016.
15.
Saied Hemati, François Leduc-Primeau, Warren J. Gross, "A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes", IEEE Communications Letters, vol.20, no.3, pp.422-425, 2016.
16.
Ioannis Tsatsaragkos, Vassilis Paliouras, "Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.62, no.8, pp.766-770, 2015.
17.
Dirk Wubben, Peter Rost, Jens Steven Bartelt, Massinissa Lalam, Valentin Savin, Matteo Gorgoglione, Armin Dekorsy, Gerhard Fettweis, "Benefits and Impact of Cloud Computing on 5G Signal Processing: Flexible centralization through cloud-RAN", IEEE Signal Processing Magazine, vol.31, no.6, pp.35-44, 2014.
18.
Fabián Angarita, Javier Valls, Vicenç Almenar, Vicente Torres, "Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, no.7, pp.2150-2158, 2014.
19.
Chiu-Wing Sham, Xu Chen, Francis C. M. Lau, Yue Zhao, Wai M. Tam, "A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.60, no.7, pp.1857-1869, 2013.
20.
Philip A. Marshall, Vincent C. Gaudet, Duncan G. Elliott, "Deeply Pipelined Digit-Serial LDPC Decoding", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, no.12, pp.2934-2944, 2012.
21.
Wojciech Sulek, "On the Overflow Problem in Finite Precision Turbo Decoding Message Passing", IEEE Transactions on Communications, vol.60, no.5, pp.1253-1259, 2012.
22.
Zhongfeng Wang, Zhiqiang Cui, Jin Sha, "VLSI Design for Low-Density Parity-Check Code Decoding", IEEE Circuits and Systems Magazine, vol.11, no.1, pp.52-69, 2011.
23.
Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, "Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, no.8, pp.1933-1943, 2011.
24.
Kai Zhang, Xinming Huang, Zhongfeng Wang, "A High-Throughput LDPC Decoder Architecture With Rate Compatibility", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, no.4, pp.839-847, 2011.
25.
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella, "Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.58, no.1, pp.98-111, 2011.
26.
Junho Cho, Jonghong Kim, Wonyong Sung, "VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.57, no.5, pp.1083-1094, 2010.

Cites in Papers - Other Publishers (17)

1.
Sivarama Prasad Tera, Rajesh Alantattil, Roy Paily, "A Flexible FPGA-Based Stochastic Decoder for 5G LDPC Codes", Electronics, vol.12, no.24, pp.4986, 2023.
2.
Muhammad Asif, Wali Ullah Khan, H. M. Rehan Afzal, Jamel Nebhen, Inam Ullah, Ateeq Ur Rehman, Mohammed K. A. Kaabar, "Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks", Wireless Communications and Mobile Computing, vol.2021, pp.1, 2021.
3.
J. Chinna Babu, C. Chinnapu Reddy, M. N. Giri Prasad, Advances in Cybernetics, Cognition, and Machine Learning for Communication Technologies, vol.643, pp.415, 2020.
4.
J. M. Catala-Perez, J. O. Lacruz, F. Garcia-Herrero, J. Valls, David Declercq, "Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes", Circuits, Systems, and Signal Processing, vol.38, no.11, pp.5068, 2019.
5.
J. Chinna Babu, C. Chinnapu Reddy, M.N. Giri Prasad, Advances in Systems, Control and Automation, vol.442, pp.605, 2018.
6.
J. Chinna Babu, C. Chinnapu Reddy, M. N. Giri Prasad, Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications, vol.434, pp.583, 2018.
7.
Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, Resource Efficient LDPC Decoders, pp.69, 2018.
8.
M.N. Giri Prasad, C. Chinnapu Reddy, J. Chinna Babu, "VLSI Implementation of decoding algorithms using EG-LDPC Codes", Procedia Computer Science, vol.115, pp.143, 2017.
9.
Chang-Kun Yao, Yun-Ching Tang, Hongchin Lin, "Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA", Journal of Circuits, Systems and Computers, vol.24, no.02, pp.1550026, 2015.
10.
Michaelraj Kingston Roberts, Ramesh Jayabalan, "A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder", Circuits, Systems, and Signal Processing, vol.34, no.6, pp.2015, 2015.
11.
O. Boncalo, A. Amaricai, V. Savin, D. Declercq, F. Ghaffari, "Check node unit for LDPC decoders based on one-hot data representation of messages", Electronics Letters, vol.51, no.12, pp.907-908, 2015.
12.
Behnam Sedighi, Hamid Khodakarami, Bipin S. G. Pillai, William Shieh, "Power-Efficiency Considerations for Adaptive Long-Haul Optical Transceivers", Journal of Optical Communications and Networking, vol.6, no.12, pp.1093, 2014.
13.
Shuangqu HUANG, Xiaoyang ZENG, Yun CHEN, "A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms", IEICE Transactions on Information and Systems, vol.E95-D, no.2, pp.403, 2012.
14.
Muhammad Awais, Carlo Condo, "Flexible LDPC Decoder Architectures", VLSI Design, vol.2012, pp.1, 2012.
15.
Srimathy Srinivasan, Andrew Thangaraj, "Codes on planar Tanner graphs", Advances in Mathematics of Communications, vol.6, no.2, pp.131, 2012.
16.
Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, "An area efficient LDPC decoder using a reduced complexity min-sum algorithm", Integration, vol.45, no.2, pp.141, 2012.
17.
Hae-Ju Kim, Kyung-Wook Shin, "Code Rate 1/2, 2304-b LDPC Decoder for IEEE 802.16e WiMAX", The Journal of Korea Information and Communications Society, vol.36, no.4A, pp.414, 2011.

References

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