Effectiveness of TMR-Based Techniques to Mitigate Alpha-Induced SEU Accumulation in Commercial SRAM-Based FPGAs | IEEE Journals & Magazine | IEEE Xplore

Effectiveness of TMR-Based Techniques to Mitigate Alpha-Induced SEU Accumulation in Commercial SRAM-Based FPGAs


Abstract:

We present an experimental analysis of alpha-induced soft errors in 90-nm low-end SRAM-based FPGAs. We first assess the relative sensitivity of the configuration memory ...Show More

Abstract:

We present an experimental analysis of alpha-induced soft errors in 90-nm low-end SRAM-based FPGAs. We first assess the relative sensitivity of the configuration memory bits controlling the different resources in the FPGA. We then study how SEU accumulation in the configuration memory impacts on the reliability of unhardened and hardened-by-design circuits. We analyze different hardening solutions comprising the use of a single voter, multiple voters, and feedback voters implemented with a commercial tool. Finally, we present an analytical model to predict the failure rate as function of the number of bit-flips in the configuration memory.
Published in: IEEE Transactions on Nuclear Science ( Volume: 55, Issue: 4, August 2008)
Page(s): 1968 - 1973
Date of Publication: 31 August 2008

ISSN Information:

References is not available for this document.

Select All
1.
M. Bellato, M. Ceschia, M. Menichelli, A. Papi, J. Wyss and A. Paccagnella, "Ion beam testing of SRAM-based FPGA's", IEEE Radiation Effects Data Workshop, 2002-Jul.
2.
A. Lesea, S. Drimer, J. Fabula, C. Carmichael and P. Alfke, "The Rosetta experiment: Atmospheric softerror rate testing in differing technology FPGAs", IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 317-328, Sep. 2005.
3.
S. Rezgui and G. M. Swift, “Virtex-II Static SEU Characterization”, 2004.
4.
M. Wirthlin, E. Johnson, N. Rollins, M. Caffrey and P. Graham, "The reliability of FPGA circuitdesigns in the presence of radiation induced configuration upsets", Proc. 11th Annu. IEEE Symp. Field-Programmable Custom Computing Machines (FCCM 2003), pp. 133-142, 2003-Apr.-9–11.
5.
E. Fuller, M. Caffrey, P. Blain, C. Carmichael, N. Khalsa and A. Salazar, "Radiation test results of the Virtex FPGAand ZBT SRAM for space based reconfigurable computing", MAPLD 1999 Proc. C_2, 1999-Sep.
6.
M. Ceschia, A. Paccagnella, S.-C. Lee, C. Wan, M. Bellato, M. Menichelli, et al., "Ion beam testing of ALTERA APEX FPGAs", IEEE NSREC 2002 Radiation Effects Data Workshop Record, 2002-Jul.
7.
H. Quinn, P. Graham, J. Krone, M. Caffrey and S. Rezgui, "Radiation-induced multi-bit upsets in SRAM-basedFPGAs", IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2455-2461, Dec. 2005.
8.
D. K. Pradhan, Fault-Tolerant Computer System Design, NJ, Englewood Cliffs:Prentice-Hall.
9.
F. Lima, C. Carmichael, J. Fabula, R. Padovani and R. Reis, "A fault injection analysis of Virtex FPGATMR design methodology", Radiation Effects on Components and Systems Conf. (RADECS2001), 2001.
10.
C. Carmichael, “Triple module redundancy design techniques for Virtex FPGAs”, Nov. 2001.
11.
L. Sterpone and M. Violante, "A new partial reconfiguration-basedfault injection system to evaluate SEU effects in SRAM-based FPGAs", IEEE Trans. Nucl. Sci..
12.
H. Quinn, K. Morgan, P. Graham, J. Krone, M. Caffrey and K. Lundgreen, "Domain crossing errors: Limitations on singledevice triple-modular redundancy circuits in Xilinx FPGAs", IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2037-2043, Dec. 2007.
13.
K. S. Morgan, D. L. McMurtrey, B. H. Pratt and M. J. Wirthlin, "A comparison of TMR with alternativefault-tolerant design techniques for FPGAs", IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2065-2072, Dec. 2007.
14.
M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, et al., "A new hardware/software platform and a new 1/E neutron sourcefor soft error studies: Testing FPGAs at the ISIS facility", IEEE Trans. Nucl. Sci., 2007.
15.
“PicoBlaze 8-Bit Embedded Microcontroller User Guide”, 2005.
16.
“TMRTool User Guide”, 2004.
17.
L. Sterpone and M. Violante, "A new reliability-orientedplace and route algorithm for SRAM-based FPGAs", IEEE Trans. Comput., vol. 55, pp. 732-744, Jun. 2006.
18.
L. Sterpone, M. Violante and S. Rezgui, "An analysis based on faultinjection of hardening techniques for SRAM-based FPGAs", IEEE Trans. Nucl. Sci., vol. 53, no. 4, pp. 2054-2059, Aug. 2006.
19.
L. Sterpone and M. Violante, "A new analytical approach toestimate the effects of SEUs in TMR architecture implemented through SRAM-basedFPGA", IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2217-2223, Dec. 2005.

References

References is not available for this document.