System structure for FPGA-based SOPC design using hard tasks

In this paper, the authors present a system structure for FPGA-based SOPC (system on programmable chip) design which uses an embedded processor to do scheduling to the HDL modules as its hard tasks. This kind of structure is implemented on the NIOS-II system offered by ALTERA and uses muC/OS-II as a real-time kernel in the embedded soft processor. The structure of the system is introduced in details on hard tasks, resources, processor and their relationships. A video capture card which is used for medical video capture and processing is also presented as an example to show the implementation and advantage of the structure for a complex embedded system.

I. Introduction

Many traditional embedded system projects are targeted at small 8 or 16 bit processors with limited resources, whereby the complexity and the requirement to sequential logic of these systems are continuously increasing [1]. This leads engineers to apply FPGA together with the processors when the developments of the processor and the real-time kernel can not keep up with the increase [2]. The underlying hypothesis is that applying such techniques will help control the complexity of the embedded systems, and improve maintainability, adaptability and portability, as well as time-to-market. To a certain extent, this structure satisfies the basal requirement of the engineers. However, the trouble of PCB wiring, the limit of code rate and the high cost of hardware come upon with this structure. To deal with these problems, much more powerful FPGAs are produced by the FPGA manufacturer. That is increasing the number of the logic gates of FPGA and embedding processor into FPGA to replace the traditional processor. Then the application of SOPC becomes feasible. The embedded processor is hardware at the very start and then replaced by software core for flexibility [3].