Abstract:
In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulatio...Show MoreMetadata
Abstract:
In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a configurable, extensible, and synthesizable window-based processing architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to previous designs. Moreover, the system performance of our window-based architecture significantly outperforms the previous designs from 7 times to 20 times.
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( Volume: 16, Issue: 8, August 2008)
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Cites in Papers - IEEE (8)
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1.
Yeong-Kang Lai, Lien-Fei Chen, Wei-Che Chiou, "A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC", IEEE Transactions on Consumer Electronics, vol.56, no.4, pp.2812-2818, 2010.
2.
Cheng-Hao Chen, Chih-Hao Chang, Kuan-Hung Chen, "High-throughput de-blocking filter accelerator for high-resolution H.264/AVC/SVC decoding", 2010 International Symposium on Next Generation Electronics, pp.211-214, 2010.
3.
Kuan-Hung Chen, Hsiang-Pin Chen, "Quadruple filtering schedule for H.264/AVC deblocking filter", Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, pp.343-346, 2010.
4.
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5.
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6.
Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, Ahsan Shabbir, "A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC", 2009 IEEE/ACM/IFIP 7th Workshop on Embedded Systems for Real-Time Multimedia, pp.18-27, 2009.
7.
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8.
Chung-Ming Chen, Chung-Ho Chen, "Configurable VLSI Architecture for Deblocking Filter in H.264/AVC", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.8, pp.1072-1082, 2008.
Cites in Papers - Other Publishers (3)
1.
Haibing Yin, Huizhu Jia, Jun Zhou, Zhiyong Gao, "Survey on Algorithm and VLSI Architecture for MPEG-Like Video Coder", Journal of Signal Processing Systems, vol.88, no.3, pp.357, 2017.
2.
M. Kthiri, B. Le Gal, P. Kadionik, A. Ben Atitallah, "A Very High Throughput Deblocking Filter for H.264/AVC", Journal of Signal Processing Systems, vol.73, no.2, pp.189, 2013.
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K.-H. Chen, "48 cycles-per-macro block deblocking filter accelerator for high-resolution H.264/AVC decoding", IET Circuits, Devices & Systems, vol.4, no.3, pp.196-206, 2010.
