Two-Dimensional Tunneling Effects on the Leakage Current of MOSFETs With Single Dielectric and High- $\kappa$ Gate Stacks

The gate leakage currents of single-gate silicon-on- insulator (SOI) n-type MOSFETs are investigated, assuming direct tunneling as the leakage mechanism and using either a 1-D Schrodinger-Poisson-based approach coupled to the conventional drift-diffusion transport model or a full quantum mechanical treatment. The first approach consists of calculating the transmission probability through the dielectric material along straight lines connecting the transistor channel to the gate. The second method is based on a 2-D Schrodinger-Poisson solver, where carriers are injected into the device from the source, drain, and gate contacts. The simulated structures have a physical gate length of 32 nm. The channel is isolated from the gate contact by a dielectric layer with an equivalent oxide thickness of 1.2 nm. This layer is composed of either pure SiO₂ or a high-kappa SiO₂ - HfO₂ stack. Irrespective of the dielectric material, the leakage currents calculated with the 1-D approach are about one order of magnitude smaller at low gate voltages and converge toward the same value as the channel potential barrier decreases. The difference is caused by the diffraction of the electron waves at both edges of the gate contact. This peculiar 2-D behavior of the gate leakage currents, as well as the limit of the 1-D model, is discussed in this paper for various dielectric configurations.

I. Introduction

To improve the performances of electronic devices, the size of their active components is scaled down according to the International Technology Roadmap for Semiconductors (ITRS) [1]. In this context, the current bulk complementary metal–oxide–semiconductor FETs are evolving toward nanoscale ultrathin body silicon-on-insulator (SOI) structures, which suffer less from short-channel effects and offer steeper subthreshold slopes [2]. This favorable behavior is attributed to better electrostatic control obtained by reducing the thickness of the silicon body on top of the buried oxide [3]. At the same time, the thickness of the traditional gate dielectric material has been scaled down below 2 nm [4]. At this size, the gate leakage currents can reach a value of 10 [5] due to their exponential dependence on the oxide thickness. They may become the dominant leakage mechanism, deteriorate the device reliability, and cause most of the power consumption. To circumvent this problem, is replaced by “high-” dielectrics as or [6] with an equivalent oxide thickness (EOT). These materials reduce the tunneling leakage due to the larger physical thickness but provide the same gate capacitance due to their higher permittivity. However, they also exhibit an increased interfacial trap concentration as compared to and cause a degradation of the channel mobility [7]. Hence, the high- materials are often used in combination with a thin layer, forming a so-called gate stack.