Contents I. Introduction
Strained-Silicon (strained-Si) MOSFET technology is a potential candidate for sub- high-speed CMOS integrated circuits due to high carrier mobility [1]. Enhanced electron mobilities have been observed in n-MOSFET employing strained-Si. However, there are no reported experimental results on the low temperature behavior and it would be interesting to confirm from low temperature measurements how effectively the buried parasitic channel may be suppressed by the use of a graded SiGe buffer.
