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130 nm-technology, 0.25 μm2, 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications | IEEE Conference Publication | IEEE Xplore

130 nm-technology, 0.25 μm2, 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications


Abstract:

We have successfully demonstrated a world smallest 0.25 μm2 cell 1T1C 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacito...Show More

Abstract:

We have successfully demonstrated a world smallest 0.25 μm2 cell 1T1C 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new FRAM cell is suitable for a mobile SoC (System-on-a-Chip) application. This is due to realization of four metal technology required for high-speed logic devices. As a result, the remanent polarization value of 32 μC/cm2was achieved after full integration and the sensing window was evaluated to 370 mV at 85 °C, 1.3 V.
Date of Conference: 12-14 June 2007
Date Added to IEEE Xplore: 08 October 2007
Print ISBN:978-4-900784-03-1

ISSN Information:

Conference Location: Kyoto, Japan

Introduction

Ferroelectric random access memory (FRAM) has been widely pursued for not only an embedded solution but stand-alone use due to its unique advantages such as non-volatility, low power consumption and high speed particularly in write operation [1]–[3]. We had already demonstrated highly reliable 1T1C 64 Mb FRAM cell a year ago [4]. The key technologies had been a 200 nm stacked capacitor with less-damaged ferroelectric films, novel rapid thermal annealing in process integration, and a novel 1T1C reference scheme in cell architecture (i.e. a multi-reference cell equalizing scheme). As 1T1C FRAM shrinks, the decrease of cell size is inevitable, and the scaling of the capacitor stack is required. However, when the thickness of the bottom electrode reduces, an integration-related defect (PZT-popping) appears due to lack of the diffusion-barrier property, which results in a device failure. Besides, in general, as a PZT film continues to thin down, it is difficult to obtain desirable directionality in crystallinity. In this paper, we have reduced a cell-capacitor stack by introducing a glue layer between the bottom electrode and the PZT.

References

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