D. J. Jung - IEEE Xplore Author Profile

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We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Da...Show More
We demonstrate endurance characteristics of a 1T1C, 64 Mb FRAM in a real-time operational situation. To explore endurance properties in address access time tAA of 100 ns, we establish a measurement set-up that covers asymmetric pulse-chains corresponding to D1- and D0-READ/RESTORE/WRITE over a frequency range from 1.0 to 7.7 MHz. What has been achieved is that endurance cycles approximate 5.9 × 10...Show More
We discuss key technologies of 180-nm node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with metal-insulator-metal (MIM) capacitors. The key integration technologies i...Show More
We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (Metal-Insulator-Metal) capacitors. The key integration technologies i...Show More
In order to realize a cost-effective high density FRAM product over 64-Mb, it is inevitable to develop technologies for a small cell and large wafer size without degradation during full integration. We have successfully demonstrated a fully functional 0.16 μm2 capacitor size, 64-Mb, 1T1C FRAM on an 8-inch wafer by introducing new integration technologies at 150 nm technology node. One of the key t...Show More
We have successfully demonstrated a world smallest 0.25 μm2 cell 1T1C 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The ne...Show More
64 Mb FRAM with ITIC (one-transistor and one-capacitor) cell architecture has progressed greatly for a robust level of reliability. Random-single-bits appeared from package-level tests are attributed mostly to extrinsic origins (e.g. interconnection failures) rather than intrinsic ones. The extrinsic failures can be linked to two activation energies: while one is 0.27 eV originated from oxygen-vac...Show More
64 Mb FRAM with a ITIC scheme has progressed greatly for mass production in terms of a highly reliable device. For the first time, package-level reliabilities of the memory were evaluated systematically and massively. We scrutinized the device reliabilities in accelerated manners, one of which is high-temperature-operating-life (HTOL) test; and the other is high-temperature-storage (HTS) test. Ran...Show More
Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb ...Show More
Recently, technology innovation for high density and high performance FRAM has been pronounced. Among the breakthrough technologies for high density and high performance FRAM, 1T1C capacitor-on-bitline (COB) cell technology is essential because it can greatly reduce FRAM cell size compared to previous and current 2T2C FRAMs (Kinam Kim, 1999; Lee et al., 1999). Design improvement for enhanced sensi...Show More
In this paper, an etching damage-free 4 Mb ferroelectric random access memory (FRAM) integration technology was for the first time developed using ferroelectric (FE) hole capacitor structure. Since the PZT capacitors are not etched, no etching damage was generated in the novel capacitor structure. The etching process issue, which is one of most critical obstacles for scaling down FRAM device, is c...Show More
A novel sensing scheme using a gate-oxide reference cell is developed for achieving high yield of 1T1C FRAM. The sensing scheme generates highly uniform and fatigue-free reference level, and thus provides a reliable sensing margin. A novel technology to evaluate charge distribution of all memory cells is used for identifying the root causes of bit failure which are most critical factor for yield l...Show More
Recently, ferroelectric random access memory has drawn a great deal of attention due to inherent properties such as nonvolatility, long retention time, high endurance, fast access time, small cell size compared to DRAM cell size in principle, and strong resistance to /spl alpha/-particle and cosmic ray irradiation. None of the available commercial memories meet all of the properties of the ferroel...Show More