Abstract:
A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker...Show MoreMetadata
Abstract:
A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.
Published in: 2006 IEEE Asian Solid-State Circuits Conference
Date of Conference: 13-15 November 2006
Date Added to IEEE Xplore: 07 May 2007
Print ISBN:0-7803-9734-7
References is not available for this document.
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1.
R. Bagheri et al.., "An 800 MHz to 5 GHz Software-Defined Radio Receiver in 90 nm CMOS", ISSCC Dig. Of Tech. Papers, pp. 480-481, Feb. 2006
2.
D. Jakonis et al., "A 2.4 GHz RF sampling Receiver Front End in 0.18 um CMOS," IEEE J. of Solid-State Circuits, vol40, no 6, pp. 1265-1277, June. 2005
3.
R. B. Staszewski et al., "All Digital TX Frequency Synthesizer and Discrete-time Receiver for Bluetooth Radio in 130-nm CMOS," IEEE J. of Solid-State Circuits, vol39, no12, pp. 2278-2291, Dec. 2004
4.
A. Dezzani, E. Andre., "A 1.2V Dual-Mode WCDMA/GPRS Sigma Delta Modulator," ISSCC Dig. Of Tech. Papers, Feb. 2003
