Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm² core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.

I. Introduction

Making RF and analog design consistent with a time to market approach is the main challenge in the continuously evolving cellular telecommunication market. The constraint is simple: how can the cell phone be compatible with a maximum number of standards, yet remaining small, cheap and quickly available? An answer is CMOS SoC integration. If this integration is successfully achieved in a CMOS process with no specific analog option, both size and cost issues are addressed. However, the crucial point, in order to take greatest advantage of digital integration, is the design of RF functions that can be integrated with a digital core. Whereas digital IP can quickly be ported in the latest technology node, its analog counterpart needs to be specifically designed to match the technology new constraints (reduced supplies, increased flicker noise, degraded passives…).