Low Thermal Budget Processing for Sequential 3-D IC Fabrication

Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. The authors demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 degC low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below

I. Introduction

Three-Dimensional (3-D) integrated circuits [1] can be built by prefabricating the circuits on separate wafers and then aligning and bonding the thinned wafers and interconnecting the different levels with deep metal vias [2]. This process is expensive and the alignment is difficult, leading to large areas set aside for the deep metal vias. An alternative monolithic method is to fabricate devices in situ on crystalline layers above an existing circuitry. The crystalline layer can be attached by a low-temperature wafer-bonding process [3].