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Wire Density Driven Global Routing for CMP Variation and Timing | IEEE Conference Publication | IEEE Xplore

Wire Density Driven Global Routing for CMP Variation and Timing


Abstract:

In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose ...Show More

Abstract:

In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compact predictive CMP model with dummy fill, and validate it with extensive industry data. While wire density has some correlation and similarity to the conventional congestion metric, they are indeed different in the global routing context. Therefore, wire density rather than congestion should be a unified metric to improve both CMP variation and timing. The proposed wire density driven global routing is implemented in a congestion-driven global router (M. Cho and D. Z. Pan, 2006) for CMP and timing optimization. The new global router utilizes several novel techniques to reduce the wire density of CMP and timing hotspots. Our experimental results are very encouraging. The proposed algorithm improves CMP variation and timing by over 7% with negligible overhead in wirelength and even slightly better routability, compared to the pure congestion-driven global router (M. Cho and D. Z. Pan, 2006)
Date of Conference: 05-09 November 2006
Date Added to IEEE Xplore: 26 February 2007
CD:1-59593-389-1

ISSN Information:

Conference Location: San Jose, CA, USA

1 Introduction

Aggressive technology scaling has led to much higher resistance and larger coupling capacitance on interconnect. According to ITRS roadmap [16], copper dishing/erosion after Chemical-Mechanical Polishing (CMP) and scattering effect may increase resistance significantly [7], [15], [29]. Also, coupling capacitance between wires becomes dominant over ground and fringing capacitance at technology (over 60% of the total capacitance), and increases rapidly with higher wire aspect ratio of the advanced technologies [2], [26], [27]. Therefore, interconnect delay will suffer from the increased resistance and coupling capacitance more seriously in the future.

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References

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