1 Introduction
Aggressive technology scaling has led to much higher resistance and larger coupling capacitance on interconnect. According to ITRS roadmap [16], copper dishing/erosion after Chemical-Mechanical Polishing (CMP) and scattering effect may increase resistance significantly [7], [15], [29]. Also, coupling capacitance between wires becomes dominant over ground and fringing capacitance at technology (over 60% of the total capacitance), and increases rapidly with higher wire aspect ratio of the advanced technologies [2], [26], [27]. Therefore, interconnect delay will suffer from the increased resistance and coupling capacitance more seriously in the future.