Analysis of 1/f noise for CMOS with high-k gate dielectrics

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, the authors discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S_vg with technology scaling according to the ITRS roadmap based on Mikoshiba's model

Introduction

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported [1]. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S_vg with technology scaling according to the ITRS roadmap based on Mikoshiba's model. For mixed signal (MS) application, EOT of both 1.3–2.0nm and 4.5–5.5nm are necessary because the supply voltage of 1.0–1.2V and 1.8–2.5V are available for digital, RF and analog application, respectively as shown in Fig. 1. Fig. 1 Requirements for digital, RF and analog circuits Fig. 2 Process flow for CMOS with HfSiON gate dielectrics. Table I HfSiON gate dielectric conditions in our experiments

Base oxide thickness (nm)	0	2.5	4
Hf concentration (%)	50	30
HfSiO thickness (nm)	2.5	3	3.5