Abstract:
A sequential machine for which any input sequence of a specified length is a distinguishing sequence is said to be definitely diagnosable. A method is developed to obtain...Show MoreMetadata
Abstract:
A sequential machine for which any input sequence of a specified length is a distinguishing sequence is said to be definitely diagnosable. A method is developed to obtain for any arbitrary sequential machine a corresponding machine which contains the original one and which is definitely diagnosable. Similarly, these techniques are applied to embed machines which are not information lossless of finite order, or which do not have the finite-memory property, into machines which contain either of these properties. Simple and systematic techniques are presented for the construction, and the determination of the length, of the distinguishing sequences of these machines. Efficient fault-detection experiments are developed for machines possessing certain special distinguishing sequences. A procedure is proposed for the design of sequential machines such that they will possess these special sequences, and for which short fault-detection experiments can be constructed.
Published in: IEEE Transactions on Electronic Computers ( Volume: EC-16, Issue: 4, August 1967)
Resource-constrained compaction of sequential circuit test sets
S.K. Bommu,S.T. Chakradhar,K.B. Doreswamy
Fault detection in sequential circuits through functional testing
G. Buonanno,F. Fummi,D. Sciuto
Sequential circuit test generation using dynamic state traversal
M.S. Hsiao,E.M. Rudnick,J.H. Patel
Sequential Circuit Test Generation in a Genetic Algorithm Framework
E.M. Rudnick,J.H. Patel,G.S. Greenstein,T.M. Niermann
An efficient algorithm for sequential circuit test generation
T.P. Kelsey,K.K. Saluja,S.Y. Lee
Application of simple genetic algorithms to sequential circuit test generation
E.M. Rudnick,J.G. Holm,D.G. Saab,J.H. Patel
Fast sequential circuit test generation using high-level and gate-level techniques
E.M. Rudnick,R. Vietti,A. Ellis,F. Corno,P. Prinetto,M. Sonza Reorda
Application of homing sequences to synchronous sequential circuit testing
I. Pomeranz,S.M. Reddy
On the role of hardware reset in synchronous sequential circuit test generation
I. Pomeranz,S.M. Reddy
Techniques for improving the efficiency of sequential circuit test generation
Xijiang Lin,I. Pomeranz,S.M. Reddy