Abstract:
A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron appl...Show MoreMetadata
Abstract:
A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 U+03BCm PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (≤or=100Ȧ), which are self aligned to the P+ poly-Si spacers. Further reduction in the short-channel effects can be expected.
Date of Conference: 13-16 December 1992
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-0817-4
Print ISSN: 0163-1918
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