High performance deep submicron buried channel PMOSFET using P + poly-Si spacer induced self-aligned ultra shallow junctions

A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 U+03BCm PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (≤or=100Ȧ), which are self aligned to the P+ poly-Si spacers. Further reduction in the short-channel effects can be expected.