Methods for partitioning the system and performance evaluation in power-hardware-in-the-loop simulations. Part I

In this paper, the interfacing schemes for power-hardware-in-the-loop (PHIL) simulations are studied. In Part I, different simulation/hardware interfaces are introduced, and a novel interfacing scheme based on the time-variant first-order approximation of dynamics of the hardware under test (HUT) is proposed. The performances of different interfaces are compared through the decoupled simulation of first-order systems. More advanced performance evaluation methods are introduced in part II.

I. Introduction

Generally, there is only signal coupling between the hardware and the virtual system in HIL simulations. Therefore, HIL techniques are limited to control or low-power applications. PHIL, on the other hand, enables the natural coupling between the simulation software and the system hardware, hence greatly extending the applicability of the HIL experiments. In the PHIL simulation system, the simulation/hardware interface occurs at a connection where real power is virtually exchanged between the simulation software and the real hardware (in contrast to the usual case where the interface occurs at a signal connection). The structure of the PHIL system is shown in Fig. 1. Fig. 1. Structure of the PHIL system