1. Introduction

An impressive research effort has been recently devoted to the use of ultra-thin oxides in CMOS technologies in relation to either oxide leakage or reliability issues. However, so far only a few papers have discussed how extremely thin dielectrics and the proximity of the gate polysilicon can affect carrier transport in the MOSFET channel [1], [2], [3]– despite some concerns were raised by the degradation of current drivability in decananometer MOSFETs with gate oxides thinner than 1.3nm [4].