Abstract:
Conditions to achieve shallow p+-junctions with low sheet resistance by using ion implantation and rapid thermal annealing (RTA), are presented. This work shows that (jun...Show MoreMetadata
Abstract:
Conditions to achieve shallow p+-junctions with low sheet resistance by using ion implantation and rapid thermal annealing (RTA), are presented. This work shows that (junction depth) × (sheet resistivity)\rho_{s}X_{j}has a smaller value with increasing implant dose and anneal temperature (boron solubility), and decreasing implant energy. However, the value is saturated for higher doses than 1016Xjcm2, where Xjis junction depth in micrometers, and anneal temperature should be lower than 1100°C, because of considerable boron diffusion even in 10-s RTA.\rho_{s}X_{j} = 18Ω.µm is achieved by BF2+ implantation with 5 × 1015-cm-2dose at 30 keV and 1000°C RTA. The possibility of further improvement in\rho_{s}X_{j}value is discussed.
Published in: IEEE Electron Device Letters ( Volume: 7, Issue: 3, March 1986)
Citations are not available for this document.
Cites in Papers - |
Cites in Papers - IEEE (6)
Select All
1.
T. Hori, K. Kurimoto, "A new p-channel MOSFET with large-tilt-angle implanted punchthrough stopper (LATIPS)", IEEE Electron Device Letters, vol.9, no.12, pp.641-643, 1988.
2.
T. Hori, K. Kurimoto, "A new half-micron p-channel MOSFET with LATIPS (large-tilt-angle implanted punchthrough stopper)", Technical Digest., International Electron Devices Meeting, pp.394-397, 1988.
3.
T.-Q. Zhang, J.-L. Liu, X.-Y. Yang, "Migration of Fluorine Atoms and Influence on Shallow P* N Junction in BF*2 Implanted Silicon under RTA", ESSDERC '88: 18th European Solid State Device Research Conference, pp.c4-519-c4-522, 1988.
4.
Kyeong-Tae Kim, Choong-Ki Kim, "Formation of shallow p+-n junctions using boron-nitride solid diffusion source", IEEE Electron Device Letters, vol.8, no.12, pp.569-571, 1987.
5.
Tiao-Yuan Huang, W.W. Yao, R.A. Martin, A.G. Lewis, M. Koyanagi, J.Y. Chen, "A new LDD transistor with inverse-T gate structure", IEEE Electron Device Letters, vol.8, no.4, pp.151-153, 1987.
6.
K.K. Ng, W.T. Lynch, "The impact of intrinsic series resistance on MOSFET scaling", IEEE Transactions on Electron Devices, vol.34, no.3, pp.503-511, 1987.
Cites in Papers - Other Publishers (7)
1.
Shuai Zhao, Guodong Yuan, Di Zhang, Xingjun Wu, Weihua Han, "Scattering suppression at MOS interface towards high-mobility Si-based field-effect transistors", Materials Science in Semiconductor Processing, vol.138, pp.106308, 2022.
2.
A.T. Fiory, A. Stevenson, A. Agarwal, N.M. Ravindra, "Photothermal Activation of Shallow Dopants Implanted in Silicon", Journal of Electronic Materials, vol.36, no.12, pp.1735, 2007.
3.
T.Q. Zhang, J.L. Liu, Z.Y. Zhou, "Deep level defects and reverse leakage current of B F2+-implanted shallow p+ n junctions after rapid thermal annealing", Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, vol.59-60, pp.1007, 1991.
4.
R. Singh, "Rapid isothermal processing", Journal of Applied Physics, vol.63, no.8, pp.R59, 1988.
5.
Jiro Matsuo, Ichiro Kato, Hiroshi Horie, Noriaki Nakayama, Hajime Ishikawa, "Abnormal solid solution and activation behavior in Ga‐implanted Si(100)", Applied Physics Letters, vol.51, no.24, pp.2037, 1987.
6.
Michael J. Hart, Alan G. R. Evans, Gehan A. J. Amaratunga, "Transient Scanning Electron Beam Annealing Methods Used to Study Diffusion and Defects in Implanted Silicon", MRS Proceedings, vol.71, 1986.
7.
R. Singh, J. Nulman, "Development Trends in The Direction of Rapid Isothermal Processing (Rip) Dominated Silicon Integrated Circuit Fabrication", MRS Proceedings, vol.71, 1986.
