HfSiON gate dielectrics design for mixed signal CMOS

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.

Introduction

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported [1]. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss l/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S_vg with technology scaling according to the ITRS roadmap based on Mikoshiba's model.