Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough "red brick wall" emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems. In this paper, we investigate the practicality of a dense power-ground interconnect architecture developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

1. Introduction

With technology scaling, the various problems of deep submicron VLSI interconnection have become a hindrance to timing closure. The problems are mainly caused by power noise, crosstalk noise, process fluctuation, and the complexity of interconnect structures.