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H. Masuda - IEEE Xplore Author Profile
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H. Masuda

Publications
81
Citations
884
Publications by Year
19792005
Co-Authors:
Show All Co-Authors (127)
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H. Masuda

Affiliation

Semiconductor Technology Academic Research Center, Yokohama, Japan

Publication Topics

Biography

Hiroo Masuda (M'71) received the B.S. degree in applied physics and the Ph.D. degree in engineering in electric systems from Tokyo Institute of Technology, Tokyo, Japan, in 1970 and 1979, respectively.,In 1970, he joined Central Research Laboratory, Hitachi, Ltd., Tokyo. He initially was engaged in research and development of a 3-$\mu$ m MOS device and process. In 1975, he joined the MOS memory group and developed a 64-K Dynamic Memory. From 1981 to 1982, he was a Visiting Scholar at the University of Michigan, Ann Arbor. From 1982 to 1991, he was with Central Research Laboratory, Hitachi, Ltd., where he worked on semiconductor device simulation and modeling. From 1991 to 2000, he was with the Device Development Center, Hitachi Ltd., where ...
Publications
81
Citations
884
Publications by Year
19792005
Co-Authors:
Show All Co-Authors (127)
Author's Published Works

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Challenge: variability characterization and modeling for 65- to 90-nm processes

H. Masuda;S. Ohkawa;A. Kurokawa;M. Aoki

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.
Year: 2005 | Conference Paper |
In sub-100-nm processes, many physical phenomena have become critical issues in the development of processes, devices, and circuits. To achieve reasonable compromise in ASIC design, device-and process-level characterization of physical designs is a fundamental requirement. In this paper, we address topics regarding "design for variability", which are increasingly important in the 65- to 90-nm tech...Show More

Challenge: variability characterization and modeling for 65- to 90-nm processes

H. Masuda;S. Ohkawa;A. Kurokawa;M. Aoki

Year: 2005 | Conference Paper |

Approach for physical design in sub-100 nm era

H. Masuda;S. Okawa;M. Aoki

2005 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2005 | Conference Paper |
Cited by: Papers (12)
In sub-100 nm processes, various physical phenomena come up as critical red-brick in designing circuits and LSIs. We focus on design for variability (DFV) for LSI-chip design, taking within-die variations into consideration. The main approach for the purpose is a new test structure, TEG (test element group), to measure the within-die variation of elements (MOS, R, C) and ring-oscillators. The prec...Show More

Approach for physical design in sub-100 nm era

H. Masuda;S. Okawa;M. Aoki

Year: 2005 | Conference Paper |

Measurement of inner-chip variation and signal integrity by a 90-nm large-scale TEG [test element group]

M. Yamamoto;Y. Hayasi;H. Endo;H. Masuda

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.
Year: 2005 | Conference Paper |
Cited by: Papers (2)
We have developed the world's first measurement methodology for both inner chip variation and SI (signal integrity) in the same 90 nm large scale TEG (test element group = test structure). And we have successfully measured the yield of inner chip variation and also the yield of SI by a logic tester. Those two characteristics in a chip or in a wafer were evaluated in a detailed analysis, directly. ...Show More

Measurement of inner-chip variation and signal integrity by a 90-nm large-scale TEG [test element group]

M. Yamamoto;Y. Hayasi;H. Endo;H. Masuda

Year: 2005 | Conference Paper |

Assessment of a 90nm PMOS NBTI in the form of products failure rate

H. Masuda;D.G. Pierce;K. Nishitsuru;K. Machida

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.
Year: 2005 | Conference Paper |
Cited by: Papers (2)
NBTI is known to be the most critical MOS reliability issue for ppb-level product failures in giga-transistor integrated systems. A new assessment on 90 nm PMOS NBTI is presented. The new metric is based on product failure rate, which takes into account product integration. In a 90 nm technology, the product level failure rate (hazard rate) is estimated to be 3E-3 FIT @ worst case environmental co...Show More

Assessment of a 90nm PMOS NBTI in the form of products failure rate

H. Masuda;D.G. Pierce;K. Nishitsuru;K. Machida

Year: 2005 | Conference Paper |

Dummy filling methods for reducing interconnect capacitance and number of fills

A. Kurokawa;T. Kanamoto;T. Ibe;A. Kasebe;Chang Wei Fong;T. Kage;Y. Inoue;H. Masuda

Sixth international symposium on quality electronic design (isqed'05)
Year: 2005 | Conference Paper |
In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: (1) improved floating square fills, (2) floa...Show More

Dummy filling methods for reducing interconnect capacitance and number of fills

A. Kurokawa;T. Kanamoto;T. Ibe;A. Kasebe;Chang Wei Fong;T. Kage;Y. Inoue;H. Masuda

Year: 2005 | Conference Paper |

Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

A. Kurokawa;M. Yamamoto;N. Ono;T. Kage;Y. Inoue;H. Masuda

Sixth international symposium on quality electronic design (isqed'05)
Year: 2005 | Conference Paper |
Cited by: Papers (1) | Patents (1)
In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough "red brick wall" emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also proces...Show More

Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

A. Kurokawa;M. Yamamoto;N. Ono;T. Kage;Y. Inoue;H. Masuda

Year: 2005 | Conference Paper |

Efficient capacitance extraction method for interconnects with dummy fills

A. Kurokawa;T. Kanamoto;A. Kasebe;Y. Inoue;H. Masuda

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)
Year: 2004 | Conference Paper |
The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of d...Show More

Efficient capacitance extraction method for interconnects with dummy fills

A. Kurokawa;T. Kanamoto;A. Kasebe;Y. Inoue;H. Masuda

Year: 2004 | Conference Paper |

DEPOGIT: dense power-ground interconnect architecture for physical design integrity

A. Kurokawa;N. Ono;T. Kage;H. Masuda

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)
Year: 2004 | Conference Paper |
Cited by: Papers (3) | Patents (1)
In recent deep submicron VLSI design, signal integrity (SI) and power-ground integrity (PGI) have become very important to design in a short time. As a solution, we propose DEPOGIT, which is a new dense power-ground interconnect architecture that realizes more robust physical design integrity. This architecture is a method of running both the power and ground wires adjacent to the signal wires. Th...Show More

DEPOGIT: dense power-ground interconnect architecture for physical design integrity

A. Kurokawa;N. Ono;T. Kage;H. Masuda

Year: 2004 | Conference Paper |

Large-scale linear circuit simulation with an inversed inductance matrix

C. Mizuta;J. Iwai;K. Machida;T. Kage;H. Masuda

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)
Year: 2004 | Conference Paper |
Cited by: Papers (2)
We show that by using an inversed form of an inductance matrix, the current variables become no more necessary in a transient analysis. Furthermore we have invented a way to remove them even in a steady state analysis while preserving the same sparse matrix topology throughout the both analyses. The removal has brought about a sufficiently effective speed-up and stability of calculation. It opens ...Show More

Large-scale linear circuit simulation with an inversed inductance matrix

C. Mizuta;J. Iwai;K. Machida;T. Kage;H. Masuda

Year: 2004 | Conference Paper |

Variation status in 100nm CMOS process and below

K. Nagase;S.I. Ohkawa;M. Aoki;H. Masuda

Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516)
Year: 2004 | Conference Paper |
Cited by: Papers (3)
This paper addresses a new variability diagnostics and variability design methodology in the sub-100nm process era. We developed a 130nm-DMA(Device Matrix Array) test structure which diagnoses within-die device and circuit variations. And then we enhanced it for 90nm process. Our experiments show a significant increase of MOS Vth and Ids variation in 90nm process. It is found that the Vth variatio...Show More

Variation status in 100nm CMOS process and below

K. Nagase;S.I. Ohkawa;M. Aoki;H. Masuda

Year: 2004 | Conference Paper |

Design guide and process quality improvement for treatment of device variations in an LSI chip

M. Aoki;S. Ohkawa;H. Masuda

Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516)
Year: 2004 | Conference Paper |
Cited by: Papers (2)
We propose guidelines for LSI-chip design, taking the within-die variations into consideration, and for process quality improvement to suppress the variations. The autocorrelation length, /spl lambda/, of device variation is shown to be a useful measure to treat the systematic variations. We may neglect the systematic variation in chips within the range of /spl lambda/, while /spl sigma//sup 2/ of...Show More

Design guide and process quality improvement for treatment of device variations in an LSI chip

M. Aoki;S. Ohkawa;H. Masuda

Year: 2004 | Conference Paper |

A novel test-structure for detail interconnect fabric diagnosis for 90nm process

S. Akutsu;N. Ishihara;H. Masuda

Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516)
Year: 2004 | Conference Paper |
Cited by: Papers (1)
Using low-k materials is one of the important new technologies to improve circuit performance in capacitive-load rich interconnect fabric. However, it is very difficult to measure the permittivity of the low-k material in actual small pitched wires, including its statistical distribution within the die and wafer. We have already developed a technology to evaluate ILD (inter layer dielectric) dimen...Show More

A novel test-structure for detail interconnect fabric diagnosis for 90nm process

S. Akutsu;N. Ishihara;H. Masuda

Year: 2004 | Conference Paper |

Development of a 90 nm large-scale TEG for evaluation and analysis of signal integrity, yield and variation

M. Yamamoto;Y. Hayasi;H. Endo;H. Masuda

Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516)
Year: 2004 | Conference Paper |
Cited by: Papers (1)
We have developed the 90 nm TEG (Test Element Group) that has large-scale patterns which compare well to those of a SoC(system on a chip) and has 4-corner address decoders. This TEG is based on the design rules of processes that are independent of the products. We have successfully measured process yield, failure terms, failure locations and evaluated characteristic variation in a chip. The yield ...Show More

Development of a 90 nm large-scale TEG for evaluation and analysis of signal integrity, yield and variation

M. Yamamoto;Y. Hayasi;H. Endo;H. Masuda

Year: 2004 | Conference Paper |

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

S. Ohkawa;M. Aoki;H. Masuda

IEEE Transactions on Semiconductor Manufacturing
Year: 2004 | Volume: 17, Issue: 2 | Journal Article |
For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element s...Show More

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

S. Ohkawa;M. Aoki;H. Masuda

Year: 2004 | Volume: 17, Issue: 2 | Journal Article |

Development of a large-scale TEG for evaluation and analysis of yield and variation

M. Yamamoto;H. Endo;H. Masuda

IEEE Transactions on Semiconductor Manufacturing
Year: 2004 | Volume: 17, Issue: 2 | Journal Article |
We have developed the world's first large-scale test element group (TEG) with large-scale elements that accurately evaluate SoC (system on chip)-level yield and variation. To enable quick feedback on processing, address decoders on all four sides of the chip and testing programs were also developed. The TEG has a simple structure to examine pure (i.e., not oriented to products) logic-processes, yi...Show More

Development of a large-scale TEG for evaluation and analysis of yield and variation

M. Yamamoto;H. Endo;H. Masuda

Year: 2004 | Volume: 17, Issue: 2 | Journal Article |

An improved GaAs device model for the simulation of analog integrated circuit

N. Matsunaga;M. Yamamoto;Y. Hatta;H. Masuda

IEEE Transactions on Electron Devices
Year: 2003 | Volume: 50, Issue: 5 | Journal Article |
This paper describes an improved device model of GaAs MESFETs and heterojunction FETs for the design and analysis of analog integrated circuits. The proposed device model provides a new expression for the current and the capacitance of the device,which gives excellent agreements with experimental data for all regions of device operation. For the expression of the low frequency anomalies of GaAs de...Show More

An improved GaAs device model for the simulation of analog integrated circuit

N. Matsunaga;M. Yamamoto;Y. Hatta;H. Masuda

Year: 2003 | Volume: 50, Issue: 5 | Journal Article |

Development of a large-scale TEG for evaluation and analysis of yield and variation

M. Yamamoto;H. Endo;H. Masuda

International Conference on Microelectronic Test Structures, 2003.
Year: 2003 | Conference Paper |
Cited by: Papers (6)
We have developed the first TEG (Test Element Group) with large-scale patterns that compare well to those of an SoC; it also address decoders in its four corners. This TEG is based on the design rules of pure processes that are independent of the product. We have successfully measured pure process yield, failure terms, and failure locations. We evaluated characteristic chip variation, and performe...Show More

Development of a large-scale TEG for evaluation and analysis of yield and variation

M. Yamamoto;H. Endo;H. Masuda

Year: 2003 | Conference Paper |

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

S. Ohkawa;M. Aoki;H. Masuda

International Conference on Microelectronic Test Structures, 2003.
Year: 2003 | Conference Paper |
For future LSI design technology, the device matrix array (DMA), which can precisely evaluate variation in device parameters within a die, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators).Show More

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

S. Ohkawa;M. Aoki;H. Masuda

Year: 2003 | Conference Paper |

Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology

Y. Sasaki;M. Sato;M. Kuramoto;F. Kikuchi;T. Kawashima;H. Masuda;K. Yano

IEEE Journal of Solid-State Circuits
Year: 2003 | Volume: 38, Issue: 5 | Journal Article |
Cited by: Papers (4) | Patents (2)
The impact of crosstalk on delay was examined by measuring a test chip manufactured with a 0.13-μm node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: 1) consideration of degradation change dependent on relative signal arrival time over a wide range; 2) static timing analysis-based operation; and 3) quantitative estimation of the deg...Show More

Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology

Y. Sasaki;M. Sato;M. Kuramoto;F. Kikuchi;T. Kawashima;H. Masuda;K. Yano

Year: 2003 | Volume: 38, Issue: 5 | Journal Article |

Approximate formulae approach for efficient inductance extraction

A. Kurokawa;T. Sato;H. Masuda

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.
Year: 2003 | Conference Paper |
Cited by: Patents (1)
In this paper, we present a new and effective approach to the extraction of on-chip inductance, in which we apply approximate formulae. The equations are based on the assumption of filaments or bars of finite width and zero thickness and are derived through Taylor's expansion of the exact formula for mutual inductance between filaments. Despite the assumption of uniform current density in each of ...Show More

Approximate formulae approach for efficient inductance extraction

A. Kurokawa;T. Sato;H. Masuda

Year: 2003 | Conference Paper |

Design and measurement of an inductance-oscillator for analyzing inductance impact on on-chip interconnect delay

T. Sato;H. Masuda

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.
Year: 2003 | Conference Paper |
Cited by: Papers (3)
A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip interconnect delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance. A test chip...Show More

Design and measurement of an inductance-oscillator for analyzing inductance impact on on-chip interconnect delay

T. Sato;H. Masuda

Year: 2003 | Conference Paper |

Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology

Y. Sasaki;M. Satoh;M. Kuramoto;F. Kikuchi;T. Kawashima;H. Masuda;K. Yano

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)
Year: 2002 | Conference Paper |
Cited by: Papers (1) | Patents (1)
The impact of crosstalk on the delay was examined by measuring a test chip manufactured with a 0.13-/spl mu/m-node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: (1) consideration of degradation change dependent on relative-signal-arrival-time over a wide range, (2) static timing analysis (STA) based operation, and (3) quantitative e...Show More

Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology

Y. Sasaki;M. Satoh;M. Kuramoto;F. Kikuchi;T. Kawashima;H. Masuda;K. Yano

Year: 2002 | Conference Paper |

A new defect distribution metrology with a consistent discrete exponential formula and its applications

H. Sato;M. Ikota;A. Sugimoto;H. Masuda

IEEE Transactions on Semiconductor Manufacturing
Year: 1999 | Volume: 12, Issue: 4 | Journal Article |
We have proposed a novel discrete exponential distribution function, which describes a defect count distribution on wafers or chips more accurately, especially in near defect-free conditions. The conventional approach based on a gamma probability density function (g-pdf) is known to fail in expressing the defects of defect-free wafers or chips, because it always gives zero as the pdf value. Since ...Show More

A new defect distribution metrology with a consistent discrete exponential formula and its applications

H. Sato;M. Ikota;A. Sugimoto;H. Masuda

Year: 1999 | Volume: 12, Issue: 4 | Journal Article |

An efficient and accurate delay library generation with RSM [BiCMOS ASIC process]

H. Sato;Y. Ito;H. Kunitomo;H. Baba;S. Isomura;H. Masuda

1999 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD'99 (IEEE Cat. No.99TH8387)
Year: 1999 | Conference Paper |
In MPU/ASIC design with 0.2 /spl mu/m BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of CKT s...Show More

An efficient and accurate delay library generation with RSM [BiCMOS ASIC process]

H. Sato;Y. Ito;H. Kunitomo;H. Baba;S. Isomura;H. Masuda

Year: 1999 | Conference Paper |

TCAD-prototyping with new accurate worst-case definition for a 0.2 micron CMOS-ASIC process

H. Kunitomo;H. Sato;K. Tsuneno;R. Ikematsu;H. Masuda

1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)
Year: 1999 | Conference Paper |
An industrial statistical worst case modeling process for 0.2 /spl mu/m CMOS is presented. It is based on new TCAD-prototyping with efficient correlation analysis for CMOS performance goals under process variability. Since the manufacturing process undergoes ongoing improvement, well-calibrated TCAD is primary tool to construct realistic performance corner models. A robust TCAD calibration method ...Show More

TCAD-prototyping with new accurate worst-case definition for a 0.2 micron CMOS-ASIC process

H. Kunitomo;H. Sato;K. Tsuneno;R. Ikematsu;H. Masuda

Year: 1999 | Conference Paper |

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