Robustness of a selective epitaxial-growth process of silicon and its application to the fabrication of a high-quality hybrid SOI wafer

Robustness of a selective epitaxial growth of silicon is demonstrated. The process window of selectivity was estimated quantitatively using the Taguchi method and signal-to-noise ratio analysis for the first time. Both the number of the silicon nuclei on the mask layer and the growth rate of silicon on a silicon substrate were investigated as the output parameters of the Taguchi method. One of the most effective process parameters for the suppression of silicon nucleation on the mask layer without retarding the growth rate of silicon is revealed to be the flow rate of SiH/sub 2/Cl/sub 2/. By calculating the number of the silicon nuclei, which could not be detected by an available measurement method, the process window of the selectivity could be determined with which a wafer with selective epitaxial silicon layer having LSI-quality could be fabricated. A high-quality silicon-on-insulator (SOI) wafer that has both an SOI region and bulk-silicon region can be obtained, and a high-quality embedded device could be realized on the SOI wafer.

I. Introduction

Recently, demands for a system-on-chip device have been increasing rapidly [1]. It is already known that high speed and low-power transistors can be fabricated on a silicon-on-insulator (SOI) wafer [2]. However, because of the buried oxide (BOX) layer, a new fabrication process or a new design is needed for the device on an SOI wafer, which was not needed for devices on bulk silicon wafers. Some devices, such as dynamic random access memories (DRAMs) with deep trenches as a storage node, cannot easily be embedded with other devices on an SOI wafer with conventional DRAM processes for a bulk silicon wafer, because the trench depth is typically 5 to 10 , much larger than the thickness of an SOI layer. A floating body cell (FBC) is one of the candidates for embedding DRAM with SOI. However, a floating body effect [3]– [5] causes the data sensing error of the FBC and the deterioration of the DRAMs' performance.