Development of a large-scale TEG for evaluation and analysis of yield and variation

We have developed the world's first large-scale test element group (TEG) with large-scale elements that accurately evaluate SoC (system on chip)-level yield and variation. To enable quick feedback on processing, address decoders on all four sides of the chip and testing programs were also developed. The TEG has a simple structure to examine pure (i.e., not oriented to products) logic-processes, yield and variation for near-minimum DSM (deep sub-micron) design rules. We have successfully measured yield, failure mode and locations both before and after on-chip high-voltage stress. It was also demonstrated that intra-/inter-die variations in various process/device elements could be quickly diagnosed within a week. The new TEG consists of five chips designed using 130-nm CMOS technology with 100-nm physical gate lengths and five copper interconnect layers. The proposed TEG could provide a strategic standard test structure for diagnosis of SoC yield/variation, as well as a technology standard for measuring electrical dimensions and evaluating charge-up damage.

I. Introduction

IN OPTIMIZING the physical design of system on chips (SoCs), the evaluation of yield and variation is a key issue in achieving finer structures, higher integration, and greater precision in deep submicron (DSM) TABLE I Comparison Between Conventional and NewTEG. New TEG Features: Exact Yield, Process Failure Terms, Failure Location and <italic>I</italic>–<italic>V</italic> Characteristics

	Conventional		New TEG
	SRAM	Short loop	Yield Variation
failure location	bit Ο	chip ×	bit,line,layer Ο
failure term	×	Δ	Ο
characteristics	×	×	Ο
process/device	×	Ο	Ο
cell size	×6Tr.	–	Ο1Tr.
sensitivity	static	–	static
Total evaluation	×	×	Ο

technologies. Many novel test element groups (TEGs) or test structures have already been developed and reported [2]–[7], [10], [12]. These include an array of devices or layers, SRAM, DRAM, ring-oscillators, etc. In several recent reports, address-decoder circuits have also been used [2]–[5], [10]. However, yield evaluation has remained a problem. Because criteria for failure, location and characteristics are difficult to clarify, even if yield evaluation is successful, it is difficult to give a lead on production improvement. Conventional TEGs deals only with single-layer, single-inspection items. There are a few large-scale TEGs with address-decoder circuits. However, they have difficulty in identifying locations of defects from measurement data. Although there is a method for distinguishing locations using SRAM, it reportedly has problems in discriminating SRAM product defects, and is unable to obtain defect characteristics and isolation capability from standard processes. [4], [5] We report the development of the first TEG containing large-scale elements for SoC-level integration. [1] This TEG can examine yield, defects and their locations, and variations in characteristics. To achieve quick measurement and analysis, the design includes specific address decoders on all four sides of the chip. The main objective of the TEG is to provide accurate and reliable data on yield, defects and statistical variations in short TAT that can be used in innovative strategies to optimize yields and reduce variations. To produce a short TAT for process feedback, we developed programs for logic and memory testers aimed at making automatic measurements at the fabrication plant. The TEG can be considered a core strategic technology that provides solutions to the increasing difficulties encountered in DSM process development. We also propose a new electrical measurement technique for extracting relevant interconnect' dimensions, a technique for evaluating on-chip charge-up damage, and a new algorithm for Wafer Map Analysis software.