Charge trapping in MOCVD hafnium-based gate field dielectric stack structures and its impact on device performance

Threshold voltage instability and mobility degradation are significant issues for high-k dielectrics. The impact of interfacial and bulk high-k properties on these issues was investigated using Hf-based gate dielectric stacks of varying physical thickness with polysilicon electrodes. The impact of charge trapping on device performance was characterized by electrical and physical analysis. Results suggest that the bulk trapping in the high-k film contributes to the degradation of device performance.

I. Introduction

In order to meet the International Technology Roadmap for Semiconductors (ITRS) requirements for equivalen to xide thickness (EOT) and gate leakage current, the conventional gate dielectric will need to be replaced by higher dielectric constant materials [1]. Hafnium-based dielectrics are being widely investigated as potential candidates for the gate dielectric material [2], [3]. Threshold voltage instability and mobility degradation, however, have been identified as significant issues for Hf-based materials [4]–[8]. To address these issues, we investigated the electrical properties of samples referred to as hybrid stacks ( S ilicate) of various thickness with respect to charge trapping. The impact of charge trapping on device performance was characterized by conventional DC measurements, fixed-amplitude (FA) variable base and fixed-base variable amplitude (VA) charge pumping (CP) [6], Secondary Ion Mass Spectroscopy (SIMS), high resolution Transmission Electron Microscopy (HRTEM), and fast transient (FT) measurements [7], [8].