Loading web-font TeX/Math/Italic
Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model | IEEE Journals & Magazine | IEEE Xplore

Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model


Abstract:

A new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multiphonon trap-assis...Show More

Abstract:

A new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multiphonon trap-assisted tunneling as conduction mechanism, calculates the total leakage current summing the contributions of the percolation paths formed by one or more aligned traps. Spatial positions and energetic levels of traps have been randomly generated within the oxide by a random number generator which has been integrated into the model. Using this model, statistical simulations of leakage currents measured from both MOS and Flash EEPROM memory tunnel oxides have been carried out. In this way, experimental leakage current distributions can be directly reproduced, thus opening a wide range of useful applications in MOS and Flash EEPROM memory reliability prediction.
Published in: IEEE Transactions on Electron Devices ( Volume: 50, Issue: 5, May 2003)
Page(s): 1246 - 1253
Date of Publication: 15 July 2003

ISSN Information:

References is not available for this document.

I. Introduction

In the last years, the interest in studying oxide leakage current has grown significantly for two main reasons.

Select All
1.
R. Moazzami and C. Hu, "Stess-induced current in thin silicon dioxide films", IEDM Tech. Dig., pp. 139-142, 2002.
2.
S.-I. Takagi, N. Yasuda and A. Toriumi, "A new I-V model for stress-induced leakage current including inelastic tunneling", IEEE Trans. Electron Devices, vol. 46, pp. 348-354, Feb. 1999.
3.
L. Larcher, A. Paccagnella and G. Ghidini, "A new model of stress induced leakage current in gate oxides", IEEE Trans. Electron Devices, vol. 48, pp. 285-288, Feb. 2001.
4.
J. Suñe and E. Miranda, " Post soft breakdown conduction in hbox{SiO}_{2} gate oxides ", IEDM Tech. Dig., pp. 533-536, 2000.
5.
M. A. Alam, B. E. Weir and P. J. Silverman, "A study of soft and hard breakdown–Part I: Analysis of statistical percolation conductance", IEEE Trans. Electron Devices, vol. 49, pp. 232-238, Feb. 2002.
6.
M. A. Alam, B. E. Weir and P. J. Silverman, "A study of soft and hard breakdown–Part II: Principles of area thickness and voltage scaling", IEEE Trans. Electron Devices, vol. 49, pp. 239-246, Feb. 2002.
7.
R. Degraeve, B. Kaczer, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, et al., "Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin layers", IEDM Tech. Dig., pp. 121-124, 2001.
8.
F. Crupi, B. Kaczer, R. Degraeve, A. De Keersgieter and G. Groseneken, "Location and hardness of the oxied breakdown in short channel n- and p- MOSFET's", Proc. 40th IEEE-IRPS, pp. 55-59, 2002.
9.
B. Kaczer, R. Degraeve, A. De Keersgieter, K. Van de Mieroop, V. Simons and G. Groseneken, "Consistent model for short-channel nMOSFET after hard gate oxide breakdown", IEEE Trans. Electron Devices, vol. 49, pp. 507-513, Mar. 2002.
10.
R. Degraeve, G. Groseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussell, et al., "New insights in the relation between electron trap generation and the statistical properties of oxide breakdown", IEEE Trans. Electron Devices, vol. 45, pp. 904-911, 1998.
11.
B. Kaczer, R. Degraeve, M. Rasras, K. Van de Mieroop, P. J. Roussell and G. Groseneken, "Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability", IEEE Trans. Electron Devices, vol. 49, pp. 500-506, Mar. 2002.
12.
R. Degraeve, B. Kaczer, A. De Keersgieter and G. Groseneken, "Relation between breakdown mode and location in short-channel nMOSFET's and its impact on reliability specifications", IEEE Trans. Device Mater. Rel., vol. 1, pp. 163-169, Sept. 2001.
13.
J. De Blauwe, J. Van Heudt, D. Wellekens, G. Groeseneken and H. E. Maes, " SILC-related effects in flash E^{2}PROM 's-Part II: Prediction of steady-state SILC-related disturb characteristics ", IEEE Trans. Electron Devices, vol. 45, pp. 1751-1760, Aug. 1998.
14.
S. Satoh, G. Hemink, K. Hatakeyama and S. Aritome, "Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics", IEEE Trans. Electron Devices, vol. 45, pp. 482-486, Feb. 1998.
15.
L. Larcher, S. bertulu and P. Pavan, " SILC effects on E^{2}PROM memory cell reliability ", IEEE Trans. Device and Material Reliability, vol. 2, pp. 13-18, Mar. 2002.
16.
H. P. Belgal, N. Righos, I. Kalastirsky, J. J. Peterson, R. Shiner and N. Mielke, "A new reliability model for post-cycling charge retention of Flash memories", Proc. 40th IEEE-IRPS, pp. 7-20, 2002.
17.
C. Lam, T. Sunaga, Y. Igarashi, M. Ichinose, K. Kitamura, C. Willets, et al., "Anomalous low temperature charge leakage mechanism in ULSI flash memories", IEDM Tech. Dig., pp. 335-338, 2000.
18.
H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Kume, K. Okuyama, et al., "A new data retention mechanism after endurance stress on flash memory", Proc. 38th IEEE-IRPS, pp. 194-199, 2000.
19.
D. Ielmini, A. S. Spinelli, A. L. Lacaita and A. Modelli, "Equivalent cell approach for extraction of the SILC distribution in flash EEPROM cells", IEEE Electron Devices Lett., vol. 23, pp. 40-42, Jan. 2002.
20.
P. J. Kuhn, A. Hoefler, T. Harp and B. Hornung, "A reliability methodology for low temperature data retention in floating gate nonvolatile memories", Proc. 39th IEEE-IRPS, pp. 266-270, 2001.
21.
A. Modelli, F. Gilardoni, D. Ielmini and A. S. Spinelli, "A new conduction mechanism for the anomalous cells in thin oxide flash EEPROM's", Proc. 39th IEEE-IRPS, pp. 61-66, 2001.
22.
D. Ielmini, A. S. Spinelli, A. L. Lacaita and A. Modelli, "A new two-trap tunneling model for the anomalous SILC in flash memories", Proc. INFOS, pp. 39-40, 2001.
23.
F. Schuler, R. Degreave, P. Hendrickx and D. Wellekens, "Physical description of anoumaluos charge loss in floating gate based NVM's and identification of its dominant parameter", Proc. 40th IEEE-IRPS, pp. 26-33, 2002.
24.
D. Ielmini, A. S. Spinelli, A. L. Lacaita and A. Modelli, "Statistical modeling or reliability and scaling projections for flash memories", IEDM Tech. Dig., pp. 703-706, 2001.
25.
R. Degraeve, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. Van Houdt, et al., "Analitycal model for failure rate prediction due to anomalous charge loss of flash memories", IEDM Tech. Dig., pp. 699-702, 2001.
26.
G. Cellere, L. Larcher, M. G. Valentini and A. Paccagnella, "Micro breakdown in small-area ultra-thin gate oxide", IEEE Trans. Electron Devices, vol. 49, pp. 1367-1374, Aug. 2002.
27.
A. Schenk and H. Hermann, "A new model for long term charge loss in EPROM's", Ext. Abstract Int. Conf. Solid State Devices Materials (SSDM), pp. 494-496, 1994.
28.
M. Hermann and A. Schenk, "Field and high temperature dependence on the long term charge loss in erasable programmable read only memories: Measurements and modeling", J. Appl. Phys., vol. 77, no. 9, pp. 4522-4540, 1995.
29.
D. Ielmini, A. S. Spinelli, M. A. Rigamonti and A. L. Lacaita, "Modeling of SILC based on electron and hole tunneling. II. Steady-state", IEEE Trans. Electron Devices, vol. 47, pp. 1266-1272, June 2000.
30.
B. Riccò, G. Gozzi and M. Lanzoni, " Modeling and simulation of stress-induced leakage current in ultrathin hbox{SiO}_{2} films ", IEEE Trans. Electron Devices, vol. 45, pp. 1554-1560, July 1998.
Contact IEEE to Subscribe

References

References is not available for this document.