I. Introduction
While THE digital signal processing (DSP) section of a wireless handset holds thousands of transistors, the biggest challenge in a wireless handset design is often the RF section. The problem usually cited is a lack of computer-aided design (CAD) models to accurately predict the RF integrated circuit's (RFIC) performance [1]. When an RF problem occurs in the design, it is usually attributed to the CAD model, its theoretical basis being drawn into question. Yet shortcomings in the RF performance of a die are just as easily due to the RF measurements used to generate the models as to the models themselves. Recently, RF on-wafer probing has extended beyond RFICs into the world of high-speed digital integrated circuits (ICs) where clocks speeds have exceeded 1 GHz. These trends in digital and RFICs emphasize the need for reliable on-wafer RF measurements.