FCE: A Fast CGRA Architecture Exploration Framework

Conventional design space exploration (DSE) flows of Coarse-grained reconfigurable arrays (CGRAs) are based on black-box optimization methods, which are slow and ineffective. This paper proposes FCE, a fast CGRA DSE framework that presents the CGRA design space to the application data flow graph (DFG) mapper and directly employs it to explore the architecture in the mapping process. FCE achieves over 1600× speedup and better result quality than conventional DSE methods, which boosts the CGRA DSE process.

I. Introduction

Coarse-grained reconfigurable arrays (CGRAs) bring hardware designs with high flexibility, reconfigurability, and energy efficiency, making them attractive for specific application domains, such as cryptographic processing [1], [2], neural network acceleration [3], [4], and scientific computing [5], [6]. During the CGRA development, developers should evaluate and tune the design to optimize the CGRA architecture. This process is called design space exploration (DSE).