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Wenbo Yin - IEEE Xplore Author Profile
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Wenbo Yin

Publications
37
Citations
80
Publications by Year
20092024
Co-Authors:
Show All Co-Authors (53)
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Wenbo Yin

Affiliation

State Key Laboratory of Integrated Chips and Systems, Fudan University

Publication Topics

Biography

Wenbo Yin is working as an engineer with the School of Microelectronics, Fudan University. His current research interests include key-value store, embedded system design, and industrial automation.(Based on document published on 14 February 2020).
Publications
37
Citations
80
Publications by Year
20092024
Co-Authors:
Show All Co-Authors (53)
Author's Published Works

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Efficient Dynamic Memory Management for High Bandwidth Memory on FPGA

Yuwei Qu;Yiqing Mao;Wenbo Yin;Lingli Wang

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)
Year: 2024 | Conference Paper |
Efficient memory allocation is essential for highperformance computing and neural networks implemented on FPGA, particularly in scenarios demanding rapid data processing and substantial bandwidth. Traditional DDR memory often fails to meet these requirements. To address this, a dynamic memory allocator on FPGA utilizing High Bandwidth Memory (HBM) is developed. Our design includes Data Dispatch, L...Show More

Efficient Dynamic Memory Management for High Bandwidth Memory on FPGA

Yuwei Qu;Yiqing Mao;Wenbo Yin;Lingli Wang

Year: 2024 | Conference Paper |

FCE: A Fast CGRA Architecture Exploration Framework

Sichao Chen;Yiqing Mao;Yuan Dai;Xuchen Gao;Wai-Shing Luk;Wenbo Yin;Lingli Wang

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)
Year: 2024 | Conference Paper |
Conventional design space exploration (DSE) flows of Coarse-grained reconfigurable arrays (CGRAs) are based on black-box optimization methods, which are slow and ineffective. This paper proposes FCE, a fast CGRA DSE framework that presents the CGRA design space to the application data flow graph (DFG) mapper and directly employs it to explore the architecture in the mapping process. FCE achieves o...Show More

FCE: A Fast CGRA Architecture Exploration Framework

Sichao Chen;Yiqing Mao;Yuan Dai;Xuchen Gao;Wai-Shing Luk;Wenbo Yin;Lingli Wang

Year: 2024 | Conference Paper |

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design

Yiqing Mao;Xuchen Gao;Jiahang Lou;Yunhui Qiu;Wenbo Yin;Wai-Shing Luk;Lingli Wang

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2024 | Conference Paper |
Convolutional neural networks (CNNs) and transformer neural networks have been adopted in a wide range of applications such as natural language processing and computer vision. Coarse-grained reconfigurable architectures (CGRAs) are highly suitable for CNN and transformer applications due to their high flexibility and energy efficiency. However, current implementations of CGRA for CNNs and transfor...Show More

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design

Yiqing Mao;Xuchen Gao;Jiahang Lou;Yunhui Qiu;Wenbo Yin;Wai-Shing Luk;Lingli Wang

Year: 2024 | Conference Paper |

MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes

Shaoyang Sun;Boyin Jin;Jiahang Lou;Jiangnan Li;Yuhang Cao;Jingyuan Li;Chen Shen;Yuan Dai;Wenbo Yin;Wai-Shing Luk;Lingli Wang

2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Year: 2024 | Conference Paper |
Coarse-grained reconfigurable architecture (CGRA) is a type of reconfigurable computing architecture suitable for emerging applications that require dynamic compilation hardware. However, the resource utilization of existing CGRA is low due to the lack of flexibility across varied application granularity. In this paper, we propose a CGRA framework for multiple dataflow lanes (MDCRA). It supports p...Show More

MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes

Shaoyang Sun;Boyin Jin;Jiahang Lou;Jiangnan Li;Yuhang Cao;Jingyuan Li;Chen Shen;Yuan Dai;Wenbo Yin;Wai-Shing Luk;Lingli Wang

Year: 2024 | Conference Paper |

An End-to-End Agile Design Framework to Improve Energy Efficiency on CGRAs

Jiangnan Li;Yazhou Yan;Guowei Zhu;Wenbo Yin;Lingli Wang

2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Year: 2024 | Conference Paper |
In this paper, we propose a domain-specific frame-work that integrates Chisel-based Coarse-grained reconfigurable architecture (CGRA) Modeling, RTL generation, Architecture Graph Intermediate Representation (IR), dataflow graph (DFG) Mapping, interconnect exploration, and physical implementation. Within this framework, we propose an interconnect exploration flow based on a novel interconnect archi...Show More

An End-to-End Agile Design Framework to Improve Energy Efficiency on CGRAs

Jiangnan Li;Yazhou Yan;Guowei Zhu;Wenbo Yin;Lingli Wang

Year: 2024 | Conference Paper |

CDE: A Novel CGRA Development Environment with Fast Design Space Exploration Framework

Sichao Chen;Yuan Dai;Jide Zhang;Huizhen Kuang;Xuchen Gao;Wai-Shing Luk;Wenbo Yin;Lingli Wang

2024 2nd International Symposium of Electronics Design Automation (ISEDA)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
The Coarse-grained reconfigurable array (CGRA) hardware design optimization is hampered by time-consuming design exploration and evaluation methods. This paper proposes CDE, a novel CGRA Development Environment with a graph-analysis-based fast design space exploration (DSE) framework and an accurate hardware evaluation tool. CDE significantly improves the efficiency of CGRA architecture developmen...Show More

CDE: A Novel CGRA Development Environment with Fast Design Space Exploration Framework

Sichao Chen;Yuan Dai;Jide Zhang;Huizhen Kuang;Xuchen Gao;Wai-Shing Luk;Wenbo Yin;Lingli Wang

Year: 2024 | Conference Paper |

TransMap: An Efficient CGRA Mapping Framework via Transformer and Deep Reinforcement Learning

Jingyuan Li;Yuan Dai;Yihan Hu;Jiangnan Li;Wenbo Yin;Jun Tao;Lingli Wang

2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Year: 2024 | Conference Paper |
Coarse-grained reconfigurable architectures (CGRAs) are garnering increasing attention as domain-specific accelerators owing to their high flexibility and energy efficiency. Mapping encompasses both placement and routing, constituting a crucial part of the CGRA toolchain. Achieving high mapping quality while minimizing mapping time has been a key objective. In this paper, we propose TransMap, an e...Show More

TransMap: An Efficient CGRA Mapping Framework via Transformer and Deep Reinforcement Learning

Jingyuan Li;Yuan Dai;Yihan Hu;Jiangnan Li;Wenbo Yin;Jun Tao;Lingli Wang

Year: 2024 | Conference Paper |

An Architecture-Agnostic Dataflow Mapping Framework on CGRA

Jiangnan Li;Yazhou Yan;Jingyuan Li;Shaoyang Sun;Boyin Jin;Wenbo Yin;Lingli Wang

2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Year: 2024 | Conference Paper |
Coarse-Grained Reconfigurable Arrays (CGRAs) are promising accelerators in the rapidly evolving field of high-performance computing (HPC). However, their potential is limited by the inability of compilers to efficiently map complex application kernels to architectures. In this paper, we propose an architecture-agnostic mapping framework called AGILE, which has a loosely coupled flow that contains ...Show More

An Architecture-Agnostic Dataflow Mapping Framework on CGRA

Jiangnan Li;Yazhou Yan;Jingyuan Li;Shaoyang Sun;Boyin Jin;Wenbo Yin;Lingli Wang

Year: 2024 | Conference Paper |

An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture

Jiahang Lou;Xuchen Gao;Yiqing Mao;Yunhui Qiu;Yihan Hu;Wenbo Yin;Lingli Wang

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Year: 2024 | Conference Paper |
Cited by: Papers (1)
Adopting specialized accelerators such as Coarse-Grained Reconfigurable Architectures (CGRAs) alongside CPUs to enhance performance within specific domains is an astute choice. However, the integration of heterogeneous architectures introduces complex challenges for compiler design. Simultaneously, the ever-expanding scale of workloads imposes substantial burdens on deployment. To address above ch...Show More

An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture

Jiahang Lou;Xuchen Gao;Yiqing Mao;Yunhui Qiu;Yihan Hu;Wenbo Yin;Lingli Wang

Year: 2024 | Conference Paper |

Data Flow Graph Partitioning Method for CGRA Temporal Mapping Based on Bayesian Optimization

Yihan Hu;Jiangnan Li;Wenbo Yin;Lingli Wang;Wai-Shing Luk

2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
Year: 2024 | Conference Paper |
Coarse-Grained Reconfigurable Arrays (CGRAs) are attracting more and more attention for their high flexibility and energy efficiency. Due to the limited resources, mapping large data flow graphs (DFGs) that represent application kernels onto a CGRA is difficult, for which partitioning is employed. However, existing partitioning methods in the CGRA domain are unable to solve large kernels. In this ...Show More

Data Flow Graph Partitioning Method for CGRA Temporal Mapping Based on Bayesian Optimization

Yihan Hu;Jiangnan Li;Wenbo Yin;Lingli Wang;Wai-Shing Luk

Year: 2024 | Conference Paper |

A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators

Xuchen Gao;Yunhui Qiu;Yuan Dai;Wenbo Yin;Lingli Wang

2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)
Year: 2024 | Conference Paper |
Coarse-grained reconfigurable architecture (CGRA) gradually becomes an extraordinarily promising accelerator due to its flexibility and power efficiency. However, most CGRA front-end compilers focus on the innermost body of regular loops with a pure data flow. Therefore, we propose CO-Compiler, an LLVM-based CGRA front-end compiler to generate an optimized control-data flow graph (CDFG), which can...Show More

A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators

Xuchen Gao;Yunhui Qiu;Yuan Dai;Wenbo Yin;Lingli Wang

Year: 2024 | Conference Paper |

HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization

Yuan Dai;Jingyuan Li;Qilong Zhu;Yunhui Qiu;Yihan Hu;Wenbo Yin;Lingli Wang

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year: 2024 | Volume: 32, Issue: 3 | Journal Article |
Cited by: Papers (1)
Due to its high energy efficiency and flexibility, coarse-grained reconfigurable architecture (CGRA) has gained increasing attention. Temporal CGRA is a typical category of CGRA that supports single-cycle context switching and time-multiplexing hardware resources to perform spatial and temporal computations. Although multiple temporal CGRAs have been proposed, an architecture with rich design para...Show More

HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization

Yuan Dai;Jingyuan Li;Qilong Zhu;Yunhui Qiu;Yihan Hu;Wenbo Yin;Lingli Wang

Year: 2024 | Volume: 32, Issue: 3 | Journal Article |

E2-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain

Yuhang Cao;Yunhui Qiu;Xuchen Gao;Qilong Zhu;Wenbo Yin;Lingli Wang

2023 International Conference on Field Programmable Technology (ICFPT)
Year: 2023 | Conference Paper |
In today’s tech-driven society, the emphasis on data privacy and security has skyrocketed. With technological progress, the emergence of new encryption algorithms and advanced attack technologies compel the need for algorithm upgrades. With rising hardware costs and demand for flexible cryptographic platforms, single-algorithm accelerators are insufficient, making versatile accelerators supporting...Show More

E2-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain

Yuhang Cao;Yunhui Qiu;Xuchen Gao;Qilong Zhu;Wenbo Yin;Lingli Wang

Year: 2023 | Conference Paper |

A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications

Qilong Zhu;Yuhang Cao;Yunhui Qiu;Xuchen Gao;Wenbo Yin;Lingli Wang

2023 International Conference on Field Programmable Technology (ICFPT)
Year: 2023 | Conference Paper |
When an application is accelerated with Coarse-Grained Reconfigurable Architecture (CGRA), it is compiled into Data Flow Graph (DFG). In conventional CGRA frameworks, only one DFG is accelerated in each epoch. Consequently, single-context CGRAs can’t fully utilize hardware resources when executing multi-kernel applications. In this paper, we propose a dynamic partial reconfigurable CGRA framework ...Show More

A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications

Qilong Zhu;Yuhang Cao;Yunhui Qiu;Xuchen Gao;Wenbo Yin;Lingli Wang

Year: 2023 | Conference Paper |

GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping

Jiangnan Li;Chang Cai;Yaya Zhao;Yazhou Yan;Wenbo Yin;Lingli Wang

2023 International Conference on Field Programmable Technology (ICFPT)
Year: 2023 | Conference Paper |
Coarse-grained reconfigurable architecture (CGRA) is an emerging computing architecture that provides a trade-off between energy efficiency and flexibility. Although the CGRA mapping problem has been explored for many years, efficiently mapping complex loop kernels to large-scale CGRAs is still challenging. In this paper, we present GRAFT, GRaph neural network (GNN) Adaptive Framework for efficien...Show More

GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping

Jiangnan Li;Chang Cai;Yaya Zhao;Yazhou Yan;Wenbo Yin;Lingli Wang

Year: 2023 | Conference Paper |

THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE

Jingyuan Li;Yunhui Qiu;Guowei Zhu;Qilong Zhu;Wenbo Yin;Lingli Wang

2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2023 | Conference Paper |
Cited by: Papers (10)
Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneous CGRA exploration framework with tunable interconnect flexibility and fast design space exploratio...Show More

THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE

Jingyuan Li;Yunhui Qiu;Guowei Zhu;Qilong Zhu;Wenbo Yin;Lingli Wang

Year: 2023 | Conference Paper |

UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization

Yuan Dai;Yunhui Qiu;Qilong Zhu;Jingyuan Li;Wenbo Yin;Lingli Wang

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Year: 2023 | Conference Paper |
Cited by: Papers (2)
Temporal Coarse-Grained Reconfigurable Architecture (CGRA) is a typical category of CGRA that supports single-cycle context switching and time-multiplexing hardware resources to perform both spatial and temporal computations. Compared with the spatial CGRA, it can be used in area and power budget-constrained scenarios, with the sacrifice of the throughput. Therefore, achieving minimum Initializati...Show More

UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization

Yuan Dai;Yunhui Qiu;Qilong Zhu;Jingyuan Li;Wenbo Yin;Lingli Wang

Year: 2023 | Conference Paper |

PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design

Bingbing Peng;Shaoyang Sun;Yuan Dai;Jingyuan Li;Yunhui Qiu;Kaihang Wang;Wenbo Yin;Lingli Wang

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Year: 2023 | Conference Paper |
Cited by: Papers (3)
Coarse-Grained Reconfigurable Architecture (CGRA) is a domain-specific reconfigurable architecture. Generally, the CGRA architecture consists of IO, memory, coarse-grained processing element (PE), and interconnect. Usually, ALU in PE contains a relatively complete set of operations and most of the interconnects adopt neighbor-to-neighbor (N2N) [1], switch-based [2], and combination of the connecti...Show More

PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design

Bingbing Peng;Shaoyang Sun;Yuan Dai;Jingyuan Li;Yunhui Qiu;Kaihang Wang;Wenbo Yin;Lingli Wang

Year: 2023 | Conference Paper |

TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework

Yunhui Qiu;Yuhang Cao;Yuan Dai;Wenbo Yin;Lingli Wang

2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2022 | Conference Paper |
Cited by: Papers (19)
Coarse-grained reconfigurable architecture (CGRA) is a promising accelerator design choice due to its high performance and power efficiency in the computation or data-intensive application domains, such as security, multimedia, digital signal processing, machine learning, and high-performance computing. CGRA consists of coarse-grained processing elements (PEs) and interconnects that determine the ...Show More

TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework

Yunhui Qiu;Yuhang Cao;Yuan Dai;Wenbo Yin;Lingli Wang

Year: 2022 | Conference Paper |

OrderMap: A CGRA Mapping Algorithm based on DFG Analysis and Graph Homomorphism

Jiangnan Li;Su Zheng;Lingli Wang;Wenbo Yin

2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
Coarse-grained reconfigurable architecture (CGRA) accelerator is a promising solution in fields such as deep learning and edge computing. One of the difficult problems to design the accelerator is to map the data flow graph (DFG) to the architecture efficiently. The previous mapping algorithms based on graph structure mainly focus on optimization during the placement and routing stage, which may f...Show More

OrderMap: A CGRA Mapping Algorithm based on DFG Analysis and Graph Homomorphism

Jiangnan Li;Su Zheng;Lingli Wang;Wenbo Yin

Year: 2022 | Conference Paper |

A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration

Yunhui Qiu;Wenbo Yin;Lingli Wang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2022 | Volume: 41, Issue: 5 | Journal Article |
Cited by: Papers (4)
Nonvolatile memory express (NVMe) is a high-performance and scalable PCI express (PCIe)-based interface for the host software communicating with NVMs, including NAND Flash and the storage class memories (SCMs). NVMe solid-state drives (SSDs) have been deployed in cloud platforms and data-centers for a variety of I/O intensive applications due to their performance benefits compared to SATA/SAS SSDs...Show More

A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration

Yunhui Qiu;Wenbo Yin;Lingli Wang

Year: 2022 | Volume: 41, Issue: 5 | Journal Article |

FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays

Su Zheng;Kaisen Zhang;Yaoguang Tian;Wenbo Yin;Lingli Wang;Xuegong Zhou

2021 International Conference on Field-Programmable Technology (ICFPT)
Year: 2021 | Conference Paper |
Cited by: Papers (6)
Coarse-Grained Reconfigurable Arrays (CGRAs) provide sufficient flexibility in domain-specific applications with high hardware efficiency, which make CGRAs suitable for fast-evolving fields such as neural network acceleration and edge computing. To meet the requirement of the fast evolution, we propose FastCGRA, the modeling, mapping, and exploration platform for large-scale CGRAs. FastCGRA suppor...Show More

FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays

Su Zheng;Kaisen Zhang;Yaoguang Tian;Wenbo Yin;Lingli Wang;Xuegong Zhou

Year: 2021 | Conference Paper |

A High-performance Open-channel Open-way NAND Flash Controller Architecture

Yunhui Qiu;Wenbo Yin;Lingli Wang

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2021 | Conference Paper |
Cited by: Papers (3)
NAND-Flash-based SSDs have been widely employed in diverse computing domains and storage systems due to their higher performance and lower power consumption than HDDs. There have been various studies to explore the internal parallelism inside SSDs, including the channel-way-plane levels of interleaving and the cache mode pipelining. However, most current studies are based on simulators or focus on...Show More

A High-performance Open-channel Open-way NAND Flash Controller Architecture

Yunhui Qiu;Wenbo Yin;Lingli Wang

Year: 2021 | Conference Paper |

Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA

Jinyu Xie;Wenbo Yin;Lingli Wang

2020 IEEE 33rd International System-on-Chip Conference (SOCC)
Year: 2020 | Conference Paper |
Cited by: Papers (3)
Load balancing is one of the most important network services in cloud data centers. However, traditional load balancers are gradually overstretched with the explosive growth of big data, whose latency and throughput are far from satisfying the performance requirements. Based on the high parallelism and flexibility of Field Programmable Gate Array (FPGA), this paper presents a load balancing scheme...Show More

Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA

Jinyu Xie;Wenbo Yin;Lingli Wang

Year: 2020 | Conference Paper |

High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator

Hankun Lv;Yuchen Ren;Yunhui Qiu;Wenbo Yin;Lingli Wang

2020 International Conference on Field-Programmable Technology (ICFPT)
Year: 2020 | Conference Paper |
This paper presents a high throughput and low latency multi-version management KVS accelerator, implemented on the FPGA-CPU heterogeneous architecture, supporting PUT, GET, DELETE and GET_RANGE operations. A pipelined Hash Engine architecture is proposed to improve the accelerator throughput and avoid data consistency issue. B-Tree processing engine is set in parallel and is designed in pipeline t...Show More

High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator

Hankun Lv;Yuchen Ren;Yunhui Qiu;Wenbo Yin;Lingli Wang

Year: 2020 | Conference Paper |

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