A low-cost 4 ps root-mean-square resolution time-todigital converter implemented in a 28 nm field-programmable gate array

This paper presents the implementation of a 28 nm field-programmable gate array (FPGA)-based time-to-digital converter (TDC), which has both high resolution and low-cost characteristics. Due to the simple TDC structure, only a few resources are required, making it suitable for multi-channel applications. An eight-channel TDC was designed in this study. In addition, an automatic nonlinearity calibration logic is implemented within the FPGA, guaranteeing stable performance of the TDC over a wide temperature range. The test results show that the average bin size of a typical channel is 2.55 ps, and the single-shot precision is better than 4 ps.